Scalar arithmetic and logic stencils#
neg_int#
STENCIL void neg_int(int arg1) {
result_int(-arg1);
}
arm64#
0000000000000000 <neg_int>:
0: 4b0003e0 neg w0, w0
4: 14000000 b 0 <result_int>
4: R_AARCH64_JUMP26 result_int
armv6#
00000000 <neg_int>:
0: e2600000 rsb r0, r0, #0
4: eafffffe b 0 <result_int>
4: R_ARM_JUMP24 result_int
armv7#
00000000 <neg_int>:
0: e2600000 rsb r0, r0, #0
4: eafffffe b 0 <result_int>
4: R_ARM_JUMP24 result_int
armv7mthumb#
00000000 <neg_int>:
0: 4240 negs r0, r0
2: f7ff bffe b.w 0 <result_int>
2: R_ARM_THM_JUMP24 result_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <neg_int>:
0: 4240 negs r0, r0
2: f7ff bffe b.w 0 <result_int>
2: R_ARM_THM_JUMP24 result_int
6: bf00 nop
armv7thumb#
00000000 <neg_int>:
0: 4240 negs r0, r0
2: f7ff bffe b.w 0 <result_int>
2: R_ARM_THM_JUMP24 result_int
6: bf00 nop
armv81mthumb#
00000000 <neg_int>:
0: 4240 negs r0, r0
2: f7ff bffe b.w 0 <result_int>
2: R_ARM_THM_JUMP24 result_int
6: bf00 nop
riscv32#
00000000 <neg_int>:
0: 40a00533 neg a0,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int
8: 00030067 jr t1 # 4 <neg_int+0x4>
riscv64#
0000000000000000 <neg_int>:
0: 40a0053b negw a0,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int
8: 00030067 jr t1 # 4 <neg_int+0x4>
tricore#
00000000 <neg_int>:
0: 32 54 rsub %d4
2: 1d 00 00 00 j 2 <neg_int+0x2>
2: R_TRICORE_24REL result_int
x86#
00000000 <neg_int>:
0: f7 5c 24 04 negl 0x4(%esp)
4: e9 fc ff ff ff jmp 5 <neg_int+0x5>
5: R_386_PC32 result_int
x86_64#
0000000000000000 <neg_int>:
0: f7 df neg %edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int-0x4
neg_float#
STENCIL void neg_float(float arg1) {
result_float(-arg1);
}
arm64#
0000000000000000 <neg_float>:
0: 1e214000 fneg s0, s0
4: 14000000 b 0 <result_float>
4: R_AARCH64_JUMP26 result_float
armv6#
00000000 <neg_float>:
0: eeb10a40 vneg.f32 s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7#
00000000 <neg_float>:
0: eeb10a40 vneg.f32 s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7mthumb#
00000000 <neg_float>:
0: eeb1 0a40 vneg.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7mthumb_fpv5#
00000000 <neg_float>:
0: eeb1 0a40 vneg.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7thumb#
00000000 <neg_float>:
0: eeb1 0a40 vneg.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv81mthumb#
00000000 <neg_float>:
0: eeb1 0a40 vneg.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
riscv32#
00000000 <neg_float>:
0: 20a51553 fneg.s fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <neg_float+0x4>
riscv64#
0000000000000000 <neg_float>:
0: 20a51553 fneg.s fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <neg_float+0x4>
tricore#
00000000 <neg_float>:
0: 9b 04 00 48 addih %d4,%d4,32768
4: 1d 00 00 00 j 4 <neg_float+0x4>
4: R_TRICORE_24REL result_float
x86#
00000000 <neg_float>:
0: d9 44 24 04 flds 0x4(%esp)
4: d9 e0 fchs
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <neg_float+0xb>
b: R_386_PC32 result_float
x86_64#
0000000000000000 <neg_float>:
0: 0f 57 05 00 00 00 00 xorps 0x0(%rip),%xmm0 # 7 <neg_float+0x7>
3: R_X86_64_PC32 .LC13-0x4
7: e9 00 00 00 00 jmp c <.LC3>
8: R_X86_64_PLT32 result_float-0x4
square_int#
STENCIL void square_int(int arg1) {
result_int(arg1 * arg1);
}
arm64#
0000000000000000 <square_int>:
0: 1b007c00 mul w0, w0, w0
4: 14000000 b 0 <result_int>
4: R_AARCH64_JUMP26 result_int
armv6#
00000000 <square_int>:
0: e0000090 mul r0, r0, r0
4: eafffffe b 0 <result_int>
4: R_ARM_JUMP24 result_int
armv7#
00000000 <square_int>:
0: e0000090 mul r0, r0, r0
4: eafffffe b 0 <result_int>
4: R_ARM_JUMP24 result_int
armv7mthumb#
00000000 <square_int>:
0: fb00 f000 mul.w r0, r0, r0
4: f7ff bffe b.w 0 <result_int>
4: R_ARM_THM_JUMP24 result_int
armv7mthumb_fpv5#
00000000 <square_int>:
0: fb00 f000 mul.w r0, r0, r0
4: f7ff bffe b.w 0 <result_int>
4: R_ARM_THM_JUMP24 result_int
armv7thumb#
00000000 <square_int>:
0: fb00 f000 mul.w r0, r0, r0
4: f7ff bffe b.w 0 <result_int>
4: R_ARM_THM_JUMP24 result_int
armv81mthumb#
00000000 <square_int>:
0: fb00 f000 mul.w r0, r0, r0
4: f7ff bffe b.w 0 <result_int>
4: R_ARM_THM_JUMP24 result_int
riscv32#
00000000 <square_int>:
0: 02a50533 mul a0,a0,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int
8: 00030067 jr t1 # 4 <square_int+0x4>
riscv64#
0000000000000000 <square_int>:
0: 02a5053b mulw a0,a0,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int
8: 00030067 jr t1 # 4 <square_int+0x4>
tricore#
00000000 <square_int>:
0: e2 44 mul %d4,%d4
2: 1d 00 00 00 j 2 <square_int+0x2>
2: R_TRICORE_24REL result_int
x86#
00000000 <square_int>:
0: 8b 44 24 04 mov 0x4(%esp),%eax
4: 0f af c0 imul %eax,%eax
7: 89 44 24 04 mov %eax,0x4(%esp)
b: e9 fc ff ff ff jmp c <square_int+0xc>
c: R_386_PC32 result_int
x86_64#
0000000000000000 <square_int>:
0: 0f af ff imul %edi,%edi
3: e9 00 00 00 00 jmp 8 <.LC2>
4: R_X86_64_PLT32 result_int-0x4
square_float#
STENCIL void square_float(float arg1) {
result_float(arg1 * arg1);
}
arm64#
0000000000000000 <square_float>:
0: 1e200800 fmul s0, s0, s0
4: 14000000 b 0 <result_float>
4: R_AARCH64_JUMP26 result_float
armv6#
00000000 <square_float>:
0: ee200a00 vmul.f32 s0, s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7#
00000000 <square_float>:
0: ee200a00 vmul.f32 s0, s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7mthumb#
00000000 <square_float>:
0: ee20 0a00 vmul.f32 s0, s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7mthumb_fpv5#
00000000 <square_float>:
0: ee20 0a00 vmul.f32 s0, s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7thumb#
00000000 <square_float>:
0: ee20 0a00 vmul.f32 s0, s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv81mthumb#
00000000 <square_float>:
0: ee20 0a00 vmul.f32 s0, s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
riscv32#
00000000 <square_float>:
0: 10a57553 fmul.s fa0,fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <square_float+0x4>
riscv64#
0000000000000000 <square_float>:
0: 10a57553 fmul.s fa0,fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <square_float+0x4>
tricore#
00000000 <square_float>:
0: 4b 44 41 40 mul.f %d4,%d4,%d4
4: 1d 00 00 00 j 4 <square_float+0x4>
4: R_TRICORE_24REL result_float
x86#
00000000 <square_float>:
0: d9 44 24 04 flds 0x4(%esp)
4: d8 c8 fmul %st(0),%st
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <square_float+0xb>
b: R_386_PC32 result_float
x86_64#
0000000000000000 <square_float>:
0: f3 0f 59 c0 mulss %xmm0,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float-0x4
abs_float#
STENCIL void abs_float(float arg1) {
result_float(fabsf((float)arg1));
}
arm64#
0000000000000000 <abs_float>:
0: 1e20c000 fabs s0, s0
4: 14000000 b 0 <result_float>
4: R_AARCH64_JUMP26 result_float
armv6#
00000000 <abs_float>:
0: eeb00ac0 vabs.f32 s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7#
00000000 <abs_float>:
0: eeb00ac0 vabs.f32 s0, s0
4: eafffffe b 0 <result_float>
4: R_ARM_JUMP24 result_float
armv7mthumb#
00000000 <abs_float>:
0: eeb0 0ac0 vabs.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7mthumb_fpv5#
00000000 <abs_float>:
0: eeb0 0ac0 vabs.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv7thumb#
00000000 <abs_float>:
0: eeb0 0ac0 vabs.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
armv81mthumb#
00000000 <abs_float>:
0: eeb0 0ac0 vabs.f32 s0, s0
4: f7ff bffe b.w 0 <result_float>
4: R_ARM_THM_JUMP24 result_float
riscv32#
00000000 <abs_float>:
0: 20a52553 fabs.s fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <abs_float+0x4>
riscv64#
0000000000000000 <abs_float>:
0: 20a52553 fabs.s fa0,fa0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float
8: 00030067 jr t1 # 4 <abs_float+0x4>
tricore#
00000000 <abs_float>:
0: b7 04 81 4f insert %d4,%d4,0,31,1
4: 1d 00 00 00 j 4 <abs_float+0x4>
4: R_TRICORE_24REL result_float
x86#
00000000 <abs_float>:
0: d9 44 24 04 flds 0x4(%esp)
4: d9 e1 fabs
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <abs_float+0xb>
b: R_386_PC32 result_float
x86_64#
0000000000000000 <abs_float>:
0: 0f 54 05 00 00 00 00 andps 0x0(%rip),%xmm0 # 7 <abs_float+0x7>
3: R_X86_64_PC32 .LC4-0x4
7: e9 00 00 00 00 jmp c <.LC3>
8: R_X86_64_PLT32 result_float-0x4
abs_int#
STENCIL void abs_int(int arg1) {
result_int(__builtin_abs(arg1));
}
arm64#
0000000000000000 <abs_int>:
0: 7100001f cmp w0, #0x0
4: 5a80a400 cneg w0, w0, lt // lt = tstop
8: 14000000 b 0 <result_int>
8: R_AARCH64_JUMP26 result_int
armv6#
00000000 <abs_int>:
0: e3500000 cmp r0, #0
4: b2600000 rsblt r0, r0, #0
8: eafffffe b 0 <result_int>
8: R_ARM_JUMP24 result_int
armv7#
00000000 <abs_int>:
0: e3500000 cmp r0, #0
4: b2600000 rsblt r0, r0, #0
8: eafffffe b 0 <result_int>
8: R_ARM_JUMP24 result_int
armv7mthumb#
00000000 <abs_int>:
0: 2800 cmp r0, #0
2: bfb8 it lt
4: 4240 neglt r0, r0
6: f7ff bffe b.w 0 <result_int>
6: R_ARM_THM_JUMP24 result_int
a: bf00 nop
armv7mthumb_fpv5#
00000000 <abs_int>:
0: 2800 cmp r0, #0
2: bfb8 it lt
4: 4240 neglt r0, r0
6: f7ff bffe b.w 0 <result_int>
6: R_ARM_THM_JUMP24 result_int
a: bf00 nop
armv7thumb#
00000000 <abs_int>:
0: 2800 cmp r0, #0
2: bfb8 it lt
4: 4240 neglt r0, r0
6: f7ff bffe b.w 0 <result_int>
6: R_ARM_THM_JUMP24 result_int
a: bf00 nop
armv81mthumb#
00000000 <abs_int>:
0: 2800 cmp r0, #0
2: bfb8 it lt
4: 4240 neglt r0, r0
6: f7ff bffe b.w 0 <result_int>
6: R_ARM_THM_JUMP24 result_int
a: bf00 nop
riscv32#
00000000 <abs_int>:
0: 41f55793 srai a5,a0,0x1f
4: 8d3d xor a0,a0,a5
6: 8d1d sub a0,a0,a5
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int
c: 00030067 jr t1 # 8 <abs_int+0x8>
riscv64#
0000000000000000 <abs_int>:
0: 41f5579b sraiw a5,a0,0x1f
4: 8d3d xor a0,a0,a5
6: 9d1d subw a0,a0,a5
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int
c: 00030067 jr t1 # 8 <abs_int+0x8>
tricore#
00000000 <abs_int>:
0: 0b 40 c0 41 abs %d4,%d4
4: 1d 00 00 00 j 4 <abs_int+0x4>
4: R_TRICORE_24REL result_int
x86#
00000000 <abs_int>:
0: 8b 54 24 04 mov 0x4(%esp),%edx
4: 89 d0 mov %edx,%eax
6: f7 d8 neg %eax
8: 0f 48 c2 cmovs %edx,%eax
b: 89 44 24 04 mov %eax,0x4(%esp)
f: e9 fc ff ff ff jmp 10 <abs_int+0x10>
10: R_386_PC32 result_int
x86_64#
0000000000000000 <abs_int>:
0: 89 f8 mov %edi,%eax
2: f7 df neg %edi
4: 0f 48 f8 cmovs %eax,%edi
7: e9 00 00 00 00 jmp c <.LC3>
8: R_X86_64_PLT32 result_int-0x4
sign_int#
STENCIL void sign_int(int arg1) {
result_int((arg1 > 0) - (arg1 < 0));
}
arm64#
0000000000000000 <sign_int>:
0: 7100001f cmp w0, #0x0
4: 1a9fd7e1 cset w1, gt
8: 4b407c20 sub w0, w1, w0, lsr #31
c: 14000000 b 0 <result_int>
c: R_AARCH64_JUMP26 result_int
armv6#
00000000 <sign_int>:
0: e1a03fa0 lsr r3, r0, #31
4: e3500000 cmp r0, #0
8: d2630000 rsble r0, r3, #0
c: c2630001 rsbgt r0, r3, #1
10: eafffffe b 0 <result_int>
10: R_ARM_JUMP24 result_int
armv7#
00000000 <sign_int>:
0: e3500000 cmp r0, #0
4: c3a03001 movgt r3, #1
8: d3a03000 movle r3, #0
c: e0430fa0 sub r0, r3, r0, lsr #31
10: eafffffe b 0 <result_int>
10: R_ARM_JUMP24 result_int
armv7mthumb#
00000000 <sign_int>:
0: 0fc3 lsrs r3, r0, #31
2: 2800 cmp r0, #0
4: bfd4 ite le
6: 4258 negle r0, r3
8: f1c3 0001 rsbgt r0, r3, #1
c: f7ff bffe b.w 0 <result_int>
c: R_ARM_THM_JUMP24 result_int
armv7mthumb_fpv5#
00000000 <sign_int>:
0: 0fc3 lsrs r3, r0, #31
2: 2800 cmp r0, #0
4: bfd4 ite le
6: 4258 negle r0, r3
8: f1c3 0001 rsbgt r0, r3, #1
c: f7ff bffe b.w 0 <result_int>
c: R_ARM_THM_JUMP24 result_int
armv7thumb#
00000000 <sign_int>:
0: 2800 cmp r0, #0
2: bfcc ite gt
4: 2301 movgt r3, #1
6: 2300 movle r3, #0
8: eba3 70d0 sub.w r0, r3, r0, lsr #31
c: f7ff bffe b.w 0 <result_int>
c: R_ARM_THM_JUMP24 result_int
armv81mthumb#
00000000 <sign_int>:
0: 0fc3 lsrs r3, r0, #31
2: 2800 cmp r0, #0
4: bfd4 ite le
6: 4258 negle r0, r3
8: f1c3 0001 rsbgt r0, r3, #1
c: f7ff bffe b.w 0 <result_int>
c: R_ARM_THM_JUMP24 result_int
riscv32#
00000000 <sign_int>:
0: 00a027b3 sgtz a5,a0
4: 817d srli a0,a0,0x1f
6: 40a78533 sub a0,a5,a0
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_int
e: 00030067 jr t1 # a <sign_int+0xa>
riscv64#
0000000000000000 <sign_int>:
0: 00a027b3 sgtz a5,a0
4: 01f5551b srliw a0,a0,0x1f
8: 40a7853b subw a0,a5,a0
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int
10: 00030067 jr t1 # c <sign_int+0xc>
tricore#
00000000 <sign_int>:
0: 02 42 mov %d2,%d4
2: 8f 12 1e 20 sh %d2,%d2,-31
6: 8b 14 80 42 ge %d4,%d4,1
a: a2 24 sub %d4,%d2
c: 1d 00 00 00 j c <sign_int+0xc>
c: R_TRICORE_24REL result_int
x86#
00000000 <sign_int>:
0: 8b 44 24 04 mov 0x4(%esp),%eax
4: 31 d2 xor %edx,%edx
6: 85 c0 test %eax,%eax
8: 0f 9f c2 setg %dl
b: c1 e8 1f shr $0x1f,%eax
e: 29 c2 sub %eax,%edx
10: 89 54 24 04 mov %edx,0x4(%esp)
14: e9 fc ff ff ff jmp 15 <sign_int+0x15>
15: R_386_PC32 result_int
x86_64#
0000000000000000 <sign_int>:
0: 31 c0 xor %eax,%eax
2: 85 ff test %edi,%edi
4: 0f 9f c0 setg %al
7: c1 ef 1f shr $0x1f,%edi
a: 29 f8 sub %edi,%eax
c: 89 c7 mov %eax,%edi
e: e9 00 00 00 00 jmp 13 <.LC13+0x3>
f: R_X86_64_PLT32 result_int-0x4
sign_float#
STENCIL void sign_float(float arg1) {
result_int((arg1 > 0) - (arg1 < 0));
}
arm64#
0000000000000000 <sign_float>:
0: 1e202018 fcmpe s0, #0.0
4: 1a9fd7e1 cset w1, gt
8: 1a9f57e0 cset w0, mi // mi = first
c: 4b000020 sub w0, w1, w0
10: 14000000 b 0 <result_int>
10: R_AARCH64_JUMP26 result_int
armv6#
00000000 <sign_float>:
0: eeb50ac0 vcmpe.f32 s0, #0.0
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: c3a00001 movgt r0, #1
c: d3a00000 movle r0, #0
10: 43a03001 movmi r3, #1
14: 53a03000 movpl r3, #0
18: e0400003 sub r0, r0, r3
1c: eafffffe b 0 <result_int>
1c: R_ARM_JUMP24 result_int
armv7#
00000000 <sign_float>:
0: eeb50ac0 vcmpe.f32 s0, #0.0
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: c3a00001 movgt r0, #1
c: d3a00000 movle r0, #0
10: 43a03001 movmi r3, #1
14: 53a03000 movpl r3, #0
18: e0400003 sub r0, r0, r3
1c: eafffffe b 0 <result_int>
1c: R_ARM_JUMP24 result_int
armv7mthumb#
00000000 <sign_float>:
0: eeb5 0ac0 vcmpe.f32 s0, #0.0
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfcc ite gt
a: 2001 movgt r0, #1
c: 2000 movle r0, #0
e: bf4c ite mi
10: 2301 movmi r3, #1
12: 2300 movpl r3, #0
14: 1ac0 subs r0, r0, r3
16: f7ff bffe b.w 0 <result_int>
16: R_ARM_THM_JUMP24 result_int
1a: bf00 nop
armv7mthumb_fpv5#
00000000 <sign_float>:
0: eeb5 0ac0 vcmpe.f32 s0, #0.0
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfcc ite gt
a: 2001 movgt r0, #1
c: 2000 movle r0, #0
e: bf4c ite mi
10: 2301 movmi r3, #1
12: 2300 movpl r3, #0
14: 1ac0 subs r0, r0, r3
16: f7ff bffe b.w 0 <result_int>
16: R_ARM_THM_JUMP24 result_int
1a: bf00 nop
armv7thumb#
00000000 <sign_float>:
0: eeb5 0ac0 vcmpe.f32 s0, #0.0
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfcc ite gt
a: 2001 movgt r0, #1
c: 2000 movle r0, #0
e: bf4c ite mi
10: 2301 movmi r3, #1
12: 2300 movpl r3, #0
14: 1ac0 subs r0, r0, r3
16: f7ff bffe b.w 0 <result_int>
16: R_ARM_THM_JUMP24 result_int
1a: bf00 nop
armv81mthumb#
00000000 <sign_float>:
0: eeb5 0ac0 vcmpe.f32 s0, #0.0
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfcc ite gt
a: 2001 movgt r0, #1
c: 2000 movle r0, #0
e: bf4c ite mi
10: 2301 movmi r3, #1
12: 2300 movpl r3, #0
14: 1ac0 subs r0, r0, r3
16: f7ff bffe b.w 0 <result_int>
16: R_ARM_THM_JUMP24 result_int
1a: bf00 nop
riscv32#
00000000 <sign_float>:
0: f00007d3 fmv.w.x fa5,zero
4: a0a79553 flt.s a0,fa5,fa0
8: a0f517d3 flt.s a5,fa0,fa5
c: 8d1d sub a0,a0,a5
e: 00000317 auipc t1,0x0
e: R_RISCV_CALL_PLT result_int
12: 00030067 jr t1 # e <sign_float+0xe>
riscv64#
0000000000000000 <sign_float>:
0: f00007d3 fmv.w.x fa5,zero
4: a0a79553 flt.s a0,fa5,fa0
8: a0f517d3 flt.s a5,fa0,fa5
c: 9d1d subw a0,a0,a5
e: 00000317 auipc t1,0x0
e: R_RISCV_CALL_PLT result_int
12: 00030067 jr t1 # e <sign_float+0xe>
tricore#
00000000 <sign_float>:
0: 82 03 mov %d3,0
2: 02 42 mov %d2,%d4
4: 4b 34 01 40 cmp.f %d4,%d4,%d3
8: 37 04 61 41 extr.u %d4,%d4,2,1
c: 4b 32 01 20 cmp.f %d2,%d2,%d3
10: 8f 12 00 21 and %d2,%d2,1
14: a2 24 sub %d4,%d2
16: 1d 00 00 00 j 16 <sign_float+0x16>
16: R_TRICORE_24REL result_int
x86#
00000000 <sign_float>:
0: d9 ee fldz
2: d9 44 24 04 flds 0x4(%esp)
6: 31 c0 xor %eax,%eax
8: db f1 fcomi %st(1),%st
a: d9 c9 fxch %st(1)
c: 0f 97 c0 seta %al
f: 31 d2 xor %edx,%edx
11: df f1 fcomip %st(1),%st
13: dd d8 fstp %st(0)
15: 0f 97 c2 seta %dl
18: 29 d0 sub %edx,%eax
1a: 89 44 24 04 mov %eax,0x4(%esp)
1e: e9 fc ff ff ff jmp 1f <sign_float+0x1f>
1f: R_386_PC32 result_int
x86_64#
0000000000000000 <sign_float>:
0: 66 0f ef c9 pxor %xmm1,%xmm1
4: 31 ff xor %edi,%edi
6: 0f 2f c1 comiss %xmm1,%xmm0
9: 40 0f 97 c7 seta %dil
d: 31 c0 xor %eax,%eax
f: 0f 2f c8 comiss %xmm0,%xmm1
12: 0f 97 c0 seta %al
15: 29 c7 sub %eax,%edi
17: e9 00 00 00 00 jmp 1c <.LC8>
18: R_X86_64_PLT32 result_int-0x4
gtabs_float_float#
STENCIL void gtabs_float_float(float arg1, float arg2) {
// Branch-free selection: int mask -1 if |arg1| > |arg2| else 0
result_int_float(-(fabsf(arg1) > fabsf(arg2)), arg2);
}
arm64#
0000000000000000 <gtabs_float_float>:
0: 7ea1ec00 facgt s0, s0, s1
4: 1e260000 fmov w0, s0
8: 1e204020 fmov s0, s1
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <gtabs_float_float>:
0: eef07ac0 vabs.f32 s15, s0
4: eeb07ae0 vabs.f32 s14, s1
8: eeb00a60 vmov.f32 s0, s1
c: eef47ac7 vcmpe.f32 s15, s14
10: eef1fa10 vmrs APSR_nzcv, fpscr
14: c3e00000 mvngt r0, #0
18: d3a00000 movle r0, #0
1c: eafffffe b 0 <result_int_float>
1c: R_ARM_JUMP24 result_int_float
armv7#
00000000 <gtabs_float_float>:
0: eef07ac0 vabs.f32 s15, s0
4: eeb07ae0 vabs.f32 s14, s1
8: eeb00a60 vmov.f32 s0, s1
c: eef47ac7 vcmpe.f32 s15, s14
10: eef1fa10 vmrs APSR_nzcv, fpscr
14: d3a00000 movle r0, #0
18: c3e00000 mvngt r0, #0
1c: eafffffe b 0 <result_int_float>
1c: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <gtabs_float_float>:
0: eeb0 0ac0 vabs.f32 s0, s0
4: eef0 7ae0 vabs.f32 s15, s1
8: eeb4 0ae7 vcmpe.f32 s0, s15
c: eef1 fa10 vmrs APSR_nzcv, fpscr
10: eeb0 0a60 vmov.f32 s0, s1
14: bfcc ite gt
16: f04f 30ff movgt.w r0, #4294967295
1a: 2000 movle r0, #0
1c: f7ff bffe b.w 0 <result_int_float>
1c: R_ARM_THM_JUMP24 result_int_float
armv7mthumb_fpv5#
00000000 <gtabs_float_float>:
0: eef0 7ac0 vabs.f32 s15, s0
4: eeb0 7ae0 vabs.f32 s14, s1
8: eeb0 0a60 vmov.f32 s0, s1
c: eef4 7ac7 vcmpe.f32 s15, s14
10: eef1 fa10 vmrs APSR_nzcv, fpscr
14: bfcc ite gt
16: f04f 30ff movgt.w r0, #4294967295
1a: 2000 movle r0, #0
1c: f7ff bffe b.w 0 <result_int_float>
1c: R_ARM_THM_JUMP24 result_int_float
armv7thumb#
00000000 <gtabs_float_float>:
0: eef0 7ac0 vabs.f32 s15, s0
4: eeb0 7ae0 vabs.f32 s14, s1
8: eeb0 0a60 vmov.f32 s0, s1
c: eef4 7ac7 vcmpe.f32 s15, s14
10: eef1 fa10 vmrs APSR_nzcv, fpscr
14: bfcc ite gt
16: f04f 30ff movgt.w r0, #4294967295
1a: 2000 movle r0, #0
1c: f7ff bffe b.w 0 <result_int_float>
1c: R_ARM_THM_JUMP24 result_int_float
armv81mthumb#
00000000 <gtabs_float_float>:
0: eef0 7ac0 vabs.f32 s15, s0
4: eeb0 7ae0 vabs.f32 s14, s1
8: eef4 7ac7 vcmpe.f32 s15, s14
c: eef1 fa10 vmrs APSR_nzcv, fpscr
10: eeb0 0a60 vmov.f32 s0, s1
14: bfcc ite gt
16: f04f 30ff movgt.w r0, #4294967295 @ 0xffffffff
1a: 2000 movle r0, #0
1c: f7ff bffe b.w 0 <result_int_float>
1c: R_ARM_THM_JUMP24 result_int_float
riscv32#
00000000 <gtabs_float_float>:
0: 20a527d3 fabs.s fa5,fa0
4: 20b5a753 fabs.s fa4,fa1
8: 20b58553 fmv.s fa0,fa1
c: a0f71553 flt.s a0,fa4,fa5
10: 40a00533 neg a0,a0
14: 00000317 auipc t1,0x0
14: R_RISCV_CALL_PLT result_int_float
18: 00030067 jr t1 # 14 <gtabs_float_float+0x14>
riscv64#
0000000000000000 <gtabs_float_float>:
0: 20a527d3 fabs.s fa5,fa0
4: 20b5a753 fabs.s fa4,fa1
8: 20b58553 fmv.s fa0,fa1
c: a0f71553 flt.s a0,fa4,fa5
10: 40a00533 neg a0,a0
14: 00000317 auipc t1,0x0
14: R_RISCV_CALL_PLT result_int_float
18: 00030067 jr t1 # 14 <gtabs_float_float+0x14>
tricore#
00000000 <gtabs_float_float>:
0: b7 04 81 4f insert %d4,%d4,0,31,1
4: b7 05 81 3f insert %d3,%d5,0,31,1
8: 4b 34 01 40 cmp.f %d4,%d4,%d3
c: 37 04 41 41 extr %d4,%d4,2,1
10: 1d 00 00 00 j 10 <gtabs_float_float+0x10>
10: R_TRICORE_24REL result_int_float
x86#
00000000 <gtabs_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: 31 c0 xor %eax,%eax
a: d9 e1 fabs
c: d9 c9 fxch %st(1)
e: d9 e1 fabs
10: d9 c9 fxch %st(1)
12: df f1 fcomip %st(1),%st
14: dd d8 fstp %st(0)
16: 0f 97 c0 seta %al
19: f7 d8 neg %eax
1b: 89 44 24 04 mov %eax,0x4(%esp)
1f: e9 fc ff ff ff jmp 20 <gtabs_float_float+0x20>
20: R_386_PC32 result_int_float
x86_64#
0000000000000000 <gtabs_float_float>:
0: f3 0f 10 15 00 00 00 movss 0x0(%rip),%xmm2 # 8 <gtabs_float_float+0x8>
7: 00
4: R_X86_64_PC32 .LC4-0x4
8: 31 ff xor %edi,%edi
a: 0f 54 c2 andps %xmm2,%xmm0
d: 0f 54 d1 andps %xmm1,%xmm2
10: 0f 2f c2 comiss %xmm2,%xmm0
13: 0f 28 c1 movaps %xmm1,%xmm0
16: 40 0f 97 c7 seta %dil
1a: f7 df neg %edi
1c: e9 00 00 00 00 jmp 21 <.LC0+0x1>
1d: R_X86_64_PLT32 result_int_float-0x4
mask_float_int#
STENCIL void mask_float_int(float arg1, int arg2) {
// Branch-free selection: arg1 where the mask arg2 is set, otherwise 0
union { float f; int i; } x = {arg1}; x.i &= arg2; result_float_int(x.f, arg2);
}
arm64#
0000000000000000 <mask_float_int>:
0: 1e270001 fmov s1, w0
4: 0e201c20 and v0.8b, v1.8b, v0.8b
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <mask_float_int>:
0: ee103a10 vmov r3, s0
4: e0033000 and r3, r3, r0
8: ee003a10 vmov s0, r3
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7#
00000000 <mask_float_int>:
0: ee103a10 vmov r3, s0
4: e0033000 and r3, r3, r0
8: ee003a10 vmov s0, r3
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <mask_float_int>:
0: ee10 3a10 vmov r3, s0
4: 4003 ands r3, r0
6: ee00 3a10 vmov s0, r3
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
armv7mthumb_fpv5#
00000000 <mask_float_int>:
0: ee10 3a10 vmov r3, s0
4: 4003 ands r3, r0
6: ee00 3a10 vmov s0, r3
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
armv7thumb#
00000000 <mask_float_int>:
0: ee10 3a10 vmov r3, s0
4: 4003 ands r3, r0
6: ee00 3a10 vmov s0, r3
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
armv81mthumb#
00000000 <mask_float_int>:
0: ee10 3a10 vmov r3, s0
4: 4003 ands r3, r0
6: ee00 3a10 vmov s0, r3
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
riscv32#
00000000 <mask_float_int>:
0: e00507d3 fmv.x.w a5,fa0
4: 8fe9 and a5,a5,a0
6: f0078553 fmv.w.x fa0,a5
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_int
e: 00030067 jr t1 # a <mask_float_int+0xa>
riscv64#
0000000000000000 <mask_float_int>:
0: e00507d3 fmv.x.w a5,fa0
4: 8fe9 and a5,a5,a0
6: f0078553 fmv.w.x fa0,a5
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_int
e: 00030067 jr t1 # a <mask_float_int+0xa>
tricore#
00000000 <mask_float_int>:
0: 26 54 and %d4,%d5
2: 1d 00 00 00 j 2 <mask_float_int+0x2>
2: R_TRICORE_24REL result_float_int
x86#
00000000 <mask_float_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 21 44 24 04 and %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <mask_float_int+0x9>
9: R_386_PC32 result_float_int
x86_64#
0000000000000000 <mask_float_int>:
0: 66 0f 7e c0 movd %xmm0,%eax
4: 21 f8 and %edi,%eax
6: 66 0f 6e c0 movd %eax,%xmm0
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_float_int-0x4
masknot_float_int#
STENCIL void masknot_float_int(float arg1, int arg2) {
// Branch-free selection: arg1 where the mask arg2 is not set, otherwise 0
union { float f; int i; } x = {arg1}; x.i &= ~arg2; result_float_int(x.f, arg2);
}
arm64#
0000000000000000 <masknot_float_int>:
0: 1e270001 fmov s1, w0
4: 0e611c00 bic v0.8b, v0.8b, v1.8b
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <masknot_float_int>:
0: ee103a10 vmov r3, s0
4: e1c33000 bic r3, r3, r0
8: ee003a10 vmov s0, r3
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7#
00000000 <masknot_float_int>:
0: ee103a10 vmov r3, s0
4: e1c33000 bic r3, r3, r0
8: ee003a10 vmov s0, r3
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <masknot_float_int>:
0: ee10 3a10 vmov r3, s0
4: ea23 0300 bic.w r3, r3, r0
8: ee00 3a10 vmov s0, r3
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
armv7mthumb_fpv5#
00000000 <masknot_float_int>:
0: ee10 3a10 vmov r3, s0
4: ea23 0300 bic.w r3, r3, r0
8: ee00 3a10 vmov s0, r3
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
armv7thumb#
00000000 <masknot_float_int>:
0: ee10 3a10 vmov r3, s0
4: ea23 0300 bic.w r3, r3, r0
8: ee00 3a10 vmov s0, r3
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
armv81mthumb#
00000000 <masknot_float_int>:
0: ee10 3a10 vmov r3, s0
4: ea23 0300 bic.w r3, r3, r0
8: ee00 3a10 vmov s0, r3
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
riscv32#
00000000 <masknot_float_int>:
0: e0050753 fmv.x.w a4,fa0
4: fff54793 not a5,a0
8: 8ff9 and a5,a5,a4
a: f0078553 fmv.w.x fa0,a5
e: 00000317 auipc t1,0x0
e: R_RISCV_CALL_PLT result_float_int
12: 00030067 jr t1 # e <masknot_float_int+0xe>
riscv64#
0000000000000000 <masknot_float_int>:
0: e0050753 fmv.x.w a4,fa0
4: fff54793 not a5,a0
8: 8ff9 and a5,a5,a4
a: f0078553 fmv.w.x fa0,a5
e: 00000317 auipc t1,0x0
e: R_RISCV_CALL_PLT result_float_int
12: 00030067 jr t1 # e <masknot_float_int+0xe>
tricore#
00000000 <masknot_float_int>:
0: 0f 54 e0 40 andn %d4,%d4,%d5
4: 1d 00 00 00 j 4 <masknot_float_int+0x4>
4: R_TRICORE_24REL result_float_int
x86#
00000000 <masknot_float_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: f7 d0 not %eax
6: 21 44 24 04 and %eax,0x4(%esp)
a: e9 fc ff ff ff jmp b <masknot_float_int+0xb>
b: R_386_PC32 result_float_int
x86_64#
0000000000000000 <masknot_float_int>:
0: 89 f8 mov %edi,%eax
2: 66 0f 7e c2 movd %xmm0,%edx
6: f7 d0 not %eax
8: 21 c2 and %eax,%edx
a: 66 0f 6e c2 movd %edx,%xmm0
e: e9 00 00 00 00 jmp 13 <.LC13+0x3>
f: R_X86_64_PLT32 result_float_int-0x4
mask_int_int#
STENCIL void mask_int_int(int arg1, int arg2) {
// Branch-free selection: arg1 where the mask arg2 is set, otherwise 0
result_int_int(arg1 & arg2, arg2);
}
arm64#
0000000000000000 <mask_int_int>:
0: 0a010000 and w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <mask_int_int>:
0: e0000001 and r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <mask_int_int>:
0: e0000001 and r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <mask_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <mask_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <mask_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <mask_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <mask_int_int>:
0: 8d6d and a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <mask_int_int+0x2>
riscv64#
0000000000000000 <mask_int_int>:
0: 8d6d and a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <mask_int_int+0x2>
tricore#
00000000 <mask_int_int>:
0: 26 54 and %d4,%d5
2: 1d 00 00 00 j 2 <mask_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <mask_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 21 44 24 04 and %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <mask_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <mask_int_int>:
0: 21 f7 and %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
masknot_int_int#
STENCIL void masknot_int_int(int arg1, int arg2) {
// Branch-free selection: arg1 where the mask arg2 is not set, otherwise 0
result_int_int(arg1 & ~arg2, arg2);
}
arm64#
0000000000000000 <masknot_int_int>:
0: 0a210000 bic w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <masknot_int_int>:
0: e1c00001 bic r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <masknot_int_int>:
0: e1c00001 bic r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <masknot_int_int>:
0: ea20 0001 bic.w r0, r0, r1
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <masknot_int_int>:
0: ea20 0001 bic.w r0, r0, r1
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <masknot_int_int>:
0: ea20 0001 bic.w r0, r0, r1
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <masknot_int_int>:
0: ea20 0001 bic.w r0, r0, r1
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <masknot_int_int>:
0: fff5c793 not a5,a1
4: 8d7d and a0,a0,a5
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <masknot_int_int+0x6>
riscv64#
0000000000000000 <masknot_int_int>:
0: fff5c793 not a5,a1
4: 8d7d and a0,a0,a5
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <masknot_int_int+0x6>
tricore#
00000000 <masknot_int_int>:
0: 0f 54 e0 40 andn %d4,%d4,%d5
4: 1d 00 00 00 j 4 <masknot_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <masknot_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: f7 d0 not %eax
6: 21 44 24 04 and %eax,0x4(%esp)
a: e9 fc ff ff ff jmp b <masknot_int_int+0xb>
b: R_386_PC32 result_int_int
x86_64#
0000000000000000 <masknot_int_int>:
0: 89 f8 mov %edi,%eax
2: 89 f7 mov %esi,%edi
4: f7 d7 not %edi
6: 21 c7 and %eax,%edi
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_int_int-0x4
min_int_int#
STENCIL void min_int_int(int a, int b) {
result_int_int(a < b ? a : b, b);
}
arm64#
0000000000000000 <min_int_int>:
0: 6b00003f cmp w1, w0
4: 1a80d020 csel w0, w1, w0, le
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <min_int_int>:
0: e1510000 cmp r1, r0
4: b1a00001 movlt r0, r1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7#
00000000 <min_int_int>:
0: e1510000 cmp r1, r0
4: b1a00001 movlt r0, r1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <min_int_int>:
0: 4288 cmp r0, r1
2: bfa8 it ge
4: 4608 movge r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7mthumb_fpv5#
00000000 <min_int_int>:
0: 4288 cmp r0, r1
2: bfa8 it ge
4: 4608 movge r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7thumb#
00000000 <min_int_int>:
0: 4288 cmp r0, r1
2: bfa8 it ge
4: 4608 movge r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv81mthumb#
00000000 <min_int_int>:
0: 4288 cmp r0, r1
2: bfa8 it ge
4: 4608 movge r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
riscv32#
00000000 <min_int_int>:
0: 87ae mv a5,a1
2: 00b55363 bge a0,a1,8 <min_int_int+0x8>
6: 87aa mv a5,a0
8: 853e mv a0,a5
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_int_int
e: 00030067 jr t1 # a <min_int_int+0xa>
riscv64#
0000000000000000 <min_int_int>:
0: 87ae mv a5,a1
2: 00b55363 bge a0,a1,8 <min_int_int+0x8>
6: 87aa mv a5,a0
8: 0007851b sext.w a0,a5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_int
10: 00030067 jr t1 # c <min_int_int+0xc>
tricore#
00000000 <min_int_int>:
0: 0b 45 80 41 min %d4,%d5,%d4
4: 1d 00 00 00 j 4 <min_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <min_int_int>:
0: 8b 54 24 04 mov 0x4(%esp),%edx
4: 8b 44 24 08 mov 0x8(%esp),%eax
8: 39 d0 cmp %edx,%eax
a: 0f 4f c2 cmovg %edx,%eax
d: 89 44 24 04 mov %eax,0x4(%esp)
11: e9 fc ff ff ff jmp 12 <min_int_int+0x12>
12: R_386_PC32 result_int_int
x86_64#
0000000000000000 <min_int_int>:
0: 39 fe cmp %edi,%esi
2: 0f 4e fe cmovle %esi,%edi
5: e9 00 00 00 00 jmp a <.LC2+0x2>
6: R_X86_64_PLT32 result_int_int-0x4
max_int_int#
STENCIL void max_int_int(int a, int b) {
result_int_int(a > b ? a : b, b);
}
arm64#
0000000000000000 <max_int_int>:
0: 6b00003f cmp w1, w0
4: 1a80a020 csel w0, w1, w0, ge // ge = tcont
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <max_int_int>:
0: e1510000 cmp r1, r0
4: a1a00001 movge r0, r1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7#
00000000 <max_int_int>:
0: e1510000 cmp r1, r0
4: a1a00001 movge r0, r1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <max_int_int>:
0: 4288 cmp r0, r1
2: bfb8 it lt
4: 4608 movlt r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7mthumb_fpv5#
00000000 <max_int_int>:
0: 4288 cmp r0, r1
2: bfb8 it lt
4: 4608 movlt r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7thumb#
00000000 <max_int_int>:
0: 4288 cmp r0, r1
2: bfb8 it lt
4: 4608 movlt r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv81mthumb#
00000000 <max_int_int>:
0: 4288 cmp r0, r1
2: bfb8 it lt
4: 4608 movlt r0, r1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
riscv32#
00000000 <max_int_int>:
0: 87ae mv a5,a1
2: 00a5d363 bge a1,a0,8 <max_int_int+0x8>
6: 87aa mv a5,a0
8: 853e mv a0,a5
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_int_int
e: 00030067 jr t1 # a <max_int_int+0xa>
riscv64#
0000000000000000 <max_int_int>:
0: 87ae mv a5,a1
2: 00a5d363 bge a1,a0,8 <max_int_int+0x8>
6: 87aa mv a5,a0
8: 0007851b sext.w a0,a5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_int
10: 00030067 jr t1 # c <max_int_int+0xc>
tricore#
00000000 <max_int_int>:
0: 0b 45 a0 41 max %d4,%d5,%d4
4: 1d 00 00 00 j 4 <max_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <max_int_int>:
0: 8b 54 24 04 mov 0x4(%esp),%edx
4: 8b 44 24 08 mov 0x8(%esp),%eax
8: 39 d0 cmp %edx,%eax
a: 0f 4c c2 cmovl %edx,%eax
d: 89 44 24 04 mov %eax,0x4(%esp)
11: e9 fc ff ff ff jmp 12 <max_int_int+0x12>
12: R_386_PC32 result_int_int
x86_64#
0000000000000000 <max_int_int>:
0: 39 fe cmp %edi,%esi
2: 0f 4d fe cmovge %esi,%edi
5: e9 00 00 00 00 jmp a <.LC2+0x2>
6: R_X86_64_PLT32 result_int_int-0x4
min_float_float#
STENCIL void min_float_float(float a, float b) {
float _a = (float)a; float _b = (float)b;
result_float_float(_a < _b ? _a : _b, b);
}
arm64#
0000000000000000 <min_float_float>:
0: 1e212010 fcmpe s0, s1
4: 1e214c00 fcsel s0, s0, s1, mi // mi = first
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <min_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: 5eb00a60 vmovpl.f32 s0, s1
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7#
00000000 <min_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: 5eb00a60 vmovpl.f32 s0, s1
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <min_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bf58 it pl
a: eeb0 0a60 vmovpl.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
armv7mthumb_fpv5#
00000000 <min_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bf58 it pl
a: eeb0 0a60 vmovpl.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
armv7thumb#
00000000 <min_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bf58 it pl
a: eeb0 0a60 vmovpl.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
armv81mthumb#
00000000 <min_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bf58 it pl
a: eeb0 0a60 vmovpl.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
riscv32#
00000000 <min_float_float>:
0: a0b517d3 flt.s a5,fa0,fa1
4: 20b587d3 fmv.s fa5,fa1
8: c399 beqz a5,e <min_float_float+0xe>
a: 20a507d3 fmv.s fa5,fa0
e: 20f78553 fmv.s fa0,fa5
12: 00000317 auipc t1,0x0
12: R_RISCV_CALL_PLT result_float_float
16: 00030067 jr t1 # 12 <min_float_float+0x12>
riscv64#
0000000000000000 <min_float_float>:
0: a0b517d3 flt.s a5,fa0,fa1
4: e399 bnez a5,a <min_float_float+0xa>
6: 20b58553 fmv.s fa0,fa1
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_float
e: 00030067 jr t1 # a <min_float_float+0xa>
tricore#
00000000 <min_float_float>:
0: 4b 54 01 20 cmp.f %d2,%d4,%d5
4: 37 02 61 20 extr.u %d2,%d2,0,1
8: 2b 54 40 42 sel %d4,%d2,%d4,%d5
c: 1d 00 00 00 j c <min_float_float+0xc>
c: R_TRICORE_24REL result_float_float
x86#
00000000 <min_float_float>:
0: d9 44 24 04 flds 0x4(%esp)
4: d9 44 24 08 flds 0x8(%esp)
8: db f1 fcomi %st(1),%st
a: d9 c9 fxch %st(1)
c: da d1 fcmovbe %st(1),%st
e: d9 c9 fxch %st(1)
10: d9 5c 24 08 fstps 0x8(%esp)
14: d9 5c 24 04 fstps 0x4(%esp)
18: e9 fc ff ff ff jmp 19 <min_float_float+0x19>
19: R_386_PC32 result_float_float
x86_64#
0000000000000000 <min_float_float>:
0: f3 0f 5d c1 minss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
max_float_float#
STENCIL void max_float_float(float a, float b) {
float _a = (float)a; float _b = (float)b;
result_float_float(_a > _b ? _a : _b, b);
}
arm64#
0000000000000000 <max_float_float>:
0: 1e212010 fcmpe s0, s1
4: 1e21cc00 fcsel s0, s0, s1, gt
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <max_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: deb00a60 vmovle.f32 s0, s1
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7#
00000000 <max_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eef1fa10 vmrs APSR_nzcv, fpscr
8: deb00a60 vmovle.f32 s0, s1
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <max_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfd8 it le
a: eeb0 0a60 vmovle.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
armv7mthumb_fpv5#
00000000 <max_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: fe30 0a20 vselgt.f32 s0, s0, s1
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <max_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: bfd8 it le
a: eeb0 0a60 vmovle.f32 s0, s1
e: f7ff bffe b.w 0 <result_float_float>
e: R_ARM_THM_JUMP24 result_float_float
12: bf00 nop
armv81mthumb#
00000000 <max_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: fe30 0a20 vselgt.f32 s0, s0, s1
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <max_float_float>:
0: a0a597d3 flt.s a5,fa1,fa0
4: 20b587d3 fmv.s fa5,fa1
8: c399 beqz a5,e <max_float_float+0xe>
a: 20a507d3 fmv.s fa5,fa0
e: 20f78553 fmv.s fa0,fa5
12: 00000317 auipc t1,0x0
12: R_RISCV_CALL_PLT result_float_float
16: 00030067 jr t1 # 12 <max_float_float+0x12>
riscv64#
0000000000000000 <max_float_float>:
0: a0a597d3 flt.s a5,fa1,fa0
4: e399 bnez a5,a <max_float_float+0xa>
6: 20b58553 fmv.s fa0,fa1
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_float
e: 00030067 jr t1 # a <max_float_float+0xa>
tricore#
00000000 <max_float_float>:
0: 4b 54 01 20 cmp.f %d2,%d4,%d5
4: 37 02 61 21 extr.u %d2,%d2,2,1
8: 2b 54 40 42 sel %d4,%d2,%d4,%d5
c: 1d 00 00 00 j c <max_float_float+0xc>
c: R_TRICORE_24REL result_float_float
x86#
00000000 <max_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: db f1 fcomi %st(1),%st
a: da d1 fcmovbe %st(1),%st
c: d9 c9 fxch %st(1)
e: d9 5c 24 08 fstps 0x8(%esp)
12: d9 5c 24 04 fstps 0x4(%esp)
16: e9 fc ff ff ff jmp 17 <max_float_float+0x17>
17: R_386_PC32 result_float_float
x86_64#
0000000000000000 <max_float_float>:
0: f3 0f 5f c1 maxss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
add_int_int#
STENCIL void add_int_int(int arg1, int arg2) {
result_int_int(arg1 + arg2, arg2);
}
arm64#
0000000000000000 <add_int_int>:
0: 0b010000 add w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <add_int_int>:
0: e0800001 add r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <add_int_int>:
0: e0800001 add r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <add_int_int>:
0: 4408 add r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <add_int_int>:
0: 4408 add r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <add_int_int>:
0: 4408 add r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <add_int_int>:
0: 4408 add r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <add_int_int>:
0: 952e add a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <add_int_int+0x2>
riscv64#
0000000000000000 <add_int_int>:
0: 9d2d addw a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <add_int_int+0x2>
tricore#
00000000 <add_int_int>:
0: 42 54 add %d4,%d5
2: 1d 00 00 00 j 2 <add_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <add_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 01 44 24 04 add %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <add_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <add_int_int>:
0: 01 f7 add %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
add_float_float#
STENCIL void add_float_float(float arg1, float arg2) {
result_float_float(arg1 + arg2, arg2);
}
arm64#
0000000000000000 <add_float_float>:
0: 1e212800 fadd s0, s0, s1
4: 14000000 b 0 <result_float_float>
4: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <add_float_float>:
0: ee300a20 vadd.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7#
00000000 <add_float_float>:
0: ee300a20 vadd.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <add_float_float>:
0: ee30 0a20 vadd.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7mthumb_fpv5#
00000000 <add_float_float>:
0: ee30 0a20 vadd.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <add_float_float>:
0: ee30 0a20 vadd.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <add_float_float>:
0: ee30 0a20 vadd.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <add_float_float>:
0: 00b57553 fadd.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <add_float_float+0x4>
riscv64#
0000000000000000 <add_float_float>:
0: 00b57553 fadd.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <add_float_float+0x4>
tricore#
00000000 <add_float_float>:
0: 6b 05 21 44 add.f %d4,%d4,%d5
4: 1d 00 00 00 j 4 <add_float_float+0x4>
4: R_TRICORE_24REL result_float_float
x86#
00000000 <add_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d8 44 24 04 fadds 0x4(%esp)
8: d9 5c 24 04 fstps 0x4(%esp)
c: e9 fc ff ff ff jmp d <add_float_float+0xd>
d: R_386_PC32 result_float_float
x86_64#
0000000000000000 <add_float_float>:
0: f3 0f 58 c1 addss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
sub_int_int#
STENCIL void sub_int_int(int arg1, int arg2) {
result_int_int(arg1 - arg2, arg2);
}
arm64#
0000000000000000 <sub_int_int>:
0: 4b010000 sub w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <sub_int_int>:
0: e0400001 sub r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <sub_int_int>:
0: e0400001 sub r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <sub_int_int>:
0: 1a40 subs r0, r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <sub_int_int>:
0: 1a40 subs r0, r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <sub_int_int>:
0: 1a40 subs r0, r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <sub_int_int>:
0: 1a40 subs r0, r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <sub_int_int>:
0: 8d0d sub a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <sub_int_int+0x2>
riscv64#
0000000000000000 <sub_int_int>:
0: 9d0d subw a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <sub_int_int+0x2>
tricore#
00000000 <sub_int_int>:
0: a2 54 sub %d4,%d5
2: 1d 00 00 00 j 2 <sub_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <sub_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 29 44 24 04 sub %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <sub_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <sub_int_int>:
0: 29 f7 sub %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
sub_float_float#
STENCIL void sub_float_float(float arg1, float arg2) {
result_float_float(arg1 - arg2, arg2);
}
arm64#
0000000000000000 <sub_float_float>:
0: 1e213800 fsub s0, s0, s1
4: 14000000 b 0 <result_float_float>
4: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <sub_float_float>:
0: ee300a60 vsub.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7#
00000000 <sub_float_float>:
0: ee300a60 vsub.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <sub_float_float>:
0: ee30 0a60 vsub.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7mthumb_fpv5#
00000000 <sub_float_float>:
0: ee30 0a60 vsub.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <sub_float_float>:
0: ee30 0a60 vsub.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <sub_float_float>:
0: ee30 0a60 vsub.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <sub_float_float>:
0: 08b57553 fsub.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <sub_float_float+0x4>
riscv64#
0000000000000000 <sub_float_float>:
0: 08b57553 fsub.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <sub_float_float+0x4>
tricore#
00000000 <sub_float_float>:
0: 6b 05 31 44 sub.f %d4,%d4,%d5
4: 1d 00 00 00 j 4 <sub_float_float+0x4>
4: R_TRICORE_24REL result_float_float
x86#
00000000 <sub_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d8 6c 24 04 fsubrs 0x4(%esp)
8: d9 5c 24 04 fstps 0x4(%esp)
c: e9 fc ff ff ff jmp d <sub_float_float+0xd>
d: R_386_PC32 result_float_float
x86_64#
0000000000000000 <sub_float_float>:
0: f3 0f 5c c1 subss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
mul_int_int#
STENCIL void mul_int_int(int arg1, int arg2) {
result_int_int(arg1 * arg2, arg2);
}
arm64#
0000000000000000 <mul_int_int>:
0: 1b017c00 mul w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <mul_int_int>:
0: e0000091 mul r0, r1, r0
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <mul_int_int>:
0: e0000091 mul r0, r1, r0
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <mul_int_int>:
0: fb01 f000 mul.w r0, r1, r0
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <mul_int_int>:
0: fb01 f000 mul.w r0, r1, r0
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <mul_int_int>:
0: fb01 f000 mul.w r0, r1, r0
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <mul_int_int>:
0: fb01 f000 mul.w r0, r1, r0
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <mul_int_int>:
0: 02b50533 mul a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <mul_int_int+0x4>
riscv64#
0000000000000000 <mul_int_int>:
0: 02b5053b mulw a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <mul_int_int+0x4>
tricore#
00000000 <mul_int_int>:
0: e2 54 mul %d4,%d5
2: 1d 00 00 00 j 2 <mul_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <mul_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 0f af 44 24 04 imul 0x4(%esp),%eax
9: 89 44 24 04 mov %eax,0x4(%esp)
d: e9 fc ff ff ff jmp e <mul_int_int+0xe>
e: R_386_PC32 result_int_int
x86_64#
0000000000000000 <mul_int_int>:
0: 0f af fe imul %esi,%edi
3: e9 00 00 00 00 jmp 8 <.LC2>
4: R_X86_64_PLT32 result_int_int-0x4
mul_float_float#
STENCIL void mul_float_float(float arg1, float arg2) {
result_float_float(arg1 * arg2, arg2);
}
arm64#
0000000000000000 <mul_float_float>:
0: 1e210800 fmul s0, s0, s1
4: 14000000 b 0 <result_float_float>
4: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <mul_float_float>:
0: ee200a20 vmul.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7#
00000000 <mul_float_float>:
0: ee200a20 vmul.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <mul_float_float>:
0: ee20 0a20 vmul.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7mthumb_fpv5#
00000000 <mul_float_float>:
0: ee20 0a20 vmul.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <mul_float_float>:
0: ee20 0a20 vmul.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <mul_float_float>:
0: ee20 0a20 vmul.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <mul_float_float>:
0: 10b57553 fmul.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <mul_float_float+0x4>
riscv64#
0000000000000000 <mul_float_float>:
0: 10b57553 fmul.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <mul_float_float+0x4>
tricore#
00000000 <mul_float_float>:
0: 4b 54 41 40 mul.f %d4,%d4,%d5
4: 1d 00 00 00 j 4 <mul_float_float+0x4>
4: R_TRICORE_24REL result_float_float
x86#
00000000 <mul_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d8 4c 24 04 fmuls 0x4(%esp)
8: d9 5c 24 04 fstps 0x4(%esp)
c: e9 fc ff ff ff jmp d <mul_float_float+0xd>
d: R_386_PC32 result_float_float
x86_64#
0000000000000000 <mul_float_float>:
0: f3 0f 59 c1 mulss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
div_float_float#
STENCIL void div_float_float(float arg1, float arg2) {
result_float_float((float)arg1 / (float)arg2, arg2);
}
arm64#
0000000000000000 <div_float_float>:
0: 1e211800 fdiv s0, s0, s1
4: 14000000 b 0 <result_float_float>
4: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <div_float_float>:
0: ee800a20 vdiv.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7#
00000000 <div_float_float>:
0: ee800a20 vdiv.f32 s0, s0, s1
4: eafffffe b 0 <result_float_float>
4: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <div_float_float>:
0: ee80 0a20 vdiv.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7mthumb_fpv5#
00000000 <div_float_float>:
0: ee80 0a20 vdiv.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <div_float_float>:
0: ee80 0a20 vdiv.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <div_float_float>:
0: ee80 0a20 vdiv.f32 s0, s0, s1
4: f7ff bffe b.w 0 <result_float_float>
4: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <div_float_float>:
0: 18b57553 fdiv.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <div_float_float+0x4>
riscv64#
0000000000000000 <div_float_float>:
0: 18b57553 fdiv.s fa0,fa0,fa1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_float_float
8: 00030067 jr t1 # 4 <div_float_float+0x4>
tricore#
00000000 <div_float_float>:
0: 4b 54 51 40 div.f %d4,%d4,%d5
4: 1d 00 00 00 j 4 <div_float_float+0x4>
4: R_TRICORE_24REL result_float_float
x86#
00000000 <div_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d8 7c 24 04 fdivrs 0x4(%esp)
8: d9 5c 24 04 fstps 0x4(%esp)
c: e9 fc ff ff ff jmp d <div_float_float+0xd>
d: R_386_PC32 result_float_float
x86_64#
0000000000000000 <div_float_float>:
0: f3 0f 5e c1 divss %xmm1,%xmm0
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_float_float-0x4
floordiv_int_int#
STENCIL void floordiv_int_int(int a, int b) {
int result = a / b - ((a % b != 0) && ((a < 0) != (b < 0)));
result_int_int(result, b);
}
arm64#
0000000000000000 <floordiv_int_int>:
0: 1ac10c03 sdiv w3, w0, w1
4: 4a010004 eor w4, w0, w1
8: 1b018062 msub w2, w3, w1, w0
c: 4b447c60 sub w0, w3, w4, lsr #31
10: 7100005f cmp w2, #0x0
14: 1a831000 csel w0, w0, w3, ne // ne = any
18: 14000000 b 0 <result_int_int>
18: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <floordiv_int_int>:
0: e92d4070 push {r4, r5, r6, lr}
4: e1a05000 mov r5, r0
8: e1a04001 mov r4, r1
c: ebfffffe bl 128 <__aeabi_idivmod>
c: R_ARM_CALL __aeabi_idivmod
10: e3510000 cmp r1, #0
14: 10255004 eorne r5, r5, r4
18: e1a01004 mov r1, r4
1c: 10400fa5 subne r0, r0, r5, lsr #31
20: e8bd4070 pop {r4, r5, r6, lr}
24: eafffffe b 0 <result_int_int>
24: R_ARM_JUMP24 result_int_int
armv7#
00000000 <floordiv_int_int>:
0: e92d4070 push {r4, r5, r6, lr}
4: e1a05000 mov r5, r0
8: e1a04001 mov r4, r1
c: ebfffffe bl 128 <__aeabi_idivmod>
c: R_ARM_CALL __aeabi_idivmod
10: e3510000 cmp r1, #0
14: 10255004 eorne r5, r5, r4
18: e1a01004 mov r1, r4
1c: 10400fa5 subne r0, r0, r5, lsr #31
20: e8bd4070 pop {r4, r5, r6, lr}
24: eafffffe b 0 <result_int_int>
24: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <floordiv_int_int>:
0: 4603 mov r3, r0
2: fb90 f0f1 sdiv r0, r0, r1
6: fb01 3210 mls r2, r1, r0, r3
a: b112 cbz r2, 12 <floordiv_int_int+0x12>
c: 404b eors r3, r1
e: eba0 70d3 sub.w r0, r0, r3, lsr #31
12: f7ff bffe b.w 0 <result_int_int>
12: R_ARM_THM_JUMP24 result_int_int
16: bf00 nop
armv7mthumb_fpv5#
00000000 <floordiv_int_int>:
0: 4603 mov r3, r0
2: fb90 f0f1 sdiv r0, r0, r1
6: fb01 3210 mls r2, r1, r0, r3
a: b112 cbz r2, 12 <floordiv_int_int+0x12>
c: 404b eors r3, r1
e: eba0 70d3 sub.w r0, r0, r3, lsr #31
12: f7ff bffe b.w 0 <result_int_int>
12: R_ARM_THM_JUMP24 result_int_int
16: bf00 nop
armv7thumb#
00000000 <floordiv_int_int>:
0: b538 push {r3, r4, r5, lr}
2: 4605 mov r5, r0
4: 460c mov r4, r1
6: f7ff fffe bl 294 <__aeabi_idivmod>
6: R_ARM_THM_CALL __aeabi_idivmod
a: b111 cbz r1, 12 <floordiv_int_int+0x12>
c: 4065 eors r5, r4
e: eba0 70d5 sub.w r0, r0, r5, lsr #31
12: 4621 mov r1, r4
14: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
18: f7ff bffe b.w 0 <result_int_int>
18: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <floordiv_int_int>:
0: 4603 mov r3, r0
2: fb90 f0f1 sdiv r0, r0, r1
6: fb01 3210 mls r2, r1, r0, r3
a: b112 cbz r2, 12 <floordiv_int_int+0x12>
c: 404b eors r3, r1
e: eba0 70d3 sub.w r0, r0, r3, lsr #31
12: f7ff bffe b.w 0 <result_int_int>
12: R_ARM_THM_JUMP24 result_int_int
16: bf00 nop
riscv32#
00000000 <floordiv_int_int>:
0: 02b56733 rem a4,a0,a1
4: 87aa mv a5,a0
6: 02b54533 div a0,a0,a1
a: c701 beqz a4,12 <floordiv_int_int+0x12>
c: 8fad xor a5,a5,a1
e: 83fd srli a5,a5,0x1f
10: 8d1d sub a0,a0,a5
12: 00000317 auipc t1,0x0
12: R_RISCV_CALL_PLT result_int_int
16: 00030067 jr t1 # 12 <floordiv_int_int+0x12>
riscv64#
0000000000000000 <floordiv_int_int>:
0: 02b566bb remw a3,a0,a1
4: 87aa mv a5,a0
6: 02b5453b divw a0,a0,a1
a: c689 beqz a3,14 <floordiv_int_int+0x14>
c: 8fad xor a5,a5,a1
e: 01f7d79b srliw a5,a5,0x1f
12: 9d1d subw a0,a0,a5
14: 00000317 auipc t1,0x0
14: R_RISCV_CALL_PLT result_int_int
18: 00030067 jr t1 # 14 <floordiv_int_int+0x14>
tricore#
00000000 <floordiv_int_int>:
0: 4b 54 01 22 div %e2,%d4,%d5
4: 02 46 mov %d6,%d4
6: 02 24 mov %d4,%d2
8: 76 33 jz %d3,e <floordiv_int_int+0xe>
a: c6 56 xor %d6,%d5
c: 0e 63 jltz %d6,12 <floordiv_int_int+0x12>
e: 1d 00 00 00 j e <floordiv_int_int+0xe>
e: R_TRICORE_24REL result_int_int
12: 1b f2 ff 4f addi %d4,%d2,-1
16: 1d 00 00 00 j 16 <floordiv_int_int+0x16>
16: R_TRICORE_24REL result_int_int
x86#
00000000 <floordiv_int_int>:
0: 53 push %ebx
1: 8b 4c 24 08 mov 0x8(%esp),%ecx
5: 8b 5c 24 0c mov 0xc(%esp),%ebx
9: 89 c8 mov %ecx,%eax
b: 99 cltd
c: f7 fb idiv %ebx
e: 85 d2 test %edx,%edx
10: 74 07 je 19 <floordiv_int_int+0x19>
12: 31 d9 xor %ebx,%ecx
14: c1 e9 1f shr $0x1f,%ecx
17: 29 c8 sub %ecx,%eax
19: 89 5c 24 0c mov %ebx,0xc(%esp)
1d: 89 44 24 08 mov %eax,0x8(%esp)
21: 5b pop %ebx
22: e9 fc ff ff ff jmp 23 <floordiv_int_int+0x23>
23: R_386_PC32 result_int_int
x86_64#
0000000000000000 <floordiv_int_int>:
0: 89 f8 mov %edi,%eax
2: 89 f9 mov %edi,%ecx
4: 99 cltd
5: f7 fe idiv %esi
7: 89 c7 mov %eax,%edi
9: 85 d2 test %edx,%edx
b: 74 07 je 14 <floordiv_int_int+0x14>
d: 31 f1 xor %esi,%ecx
f: c1 e9 1f shr $0x1f,%ecx
12: 29 cf sub %ecx,%edi
14: e9 00 00 00 00 jmp 19 <.LC27+0x1>
15: R_X86_64_PLT32 result_int_int-0x4
floordiv_float_float#
STENCIL void floordiv_float_float(float a, float b) {
result_float_float(floorf((float)a / (float)b), b);
}
arm64#
0000000000000000 <floordiv_float_float>:
0: 1e211800 fdiv s0, s0, s1
4: 1e254000 frintm s0, s0
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <floordiv_float_float>:
0: e92d4010 push {r4, lr}
4: ed2d8b02 vpush {d8}
8: eeb08a60 vmov.f32 s16, s1
c: ee800a20 vdiv.f32 s0, s0, s1
10: ebfffffe bl 0 <floordiv_float_float>
10: R_ARM_CALL floorf
14: eef00a48 vmov.f32 s1, s16
18: ecbd8b02 vpop {d8}
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_float>
20: R_ARM_JUMP24 result_float_float
armv7#
00000000 <floordiv_float_float>:
0: ee800a20 vdiv.f32 s0, s0, s1
4: e92d4010 push {r4, lr}
8: ed2d8b02 vpush {d8}
c: eeb08a60 vmov.f32 s16, s1
10: ebfffffe bl 0 <floordiv_float_float>
10: R_ARM_CALL floorf
14: eef00a48 vmov.f32 s1, s16
18: ecbd8b02 vpop {d8}
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_float>
20: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <floordiv_float_float>:
0: b508 push {r3, lr}
2: ed2d 8b02 vpush {d8}
6: ee80 0a20 vdiv.f32 s0, s0, s1
a: eeb0 8a60 vmov.f32 s16, s1
e: f7ff fffe bl 0 <floordiv_float_float>
e: R_ARM_THM_CALL floorf
12: eef0 0a48 vmov.f32 s1, s16
16: ecbd 8b02 vpop {d8}
1a: e8bd 4008 ldmia.w sp!, {r3, lr}
1e: f7ff bffe b.w 0 <result_float_float>
1e: R_ARM_THM_JUMP24 result_float_float
22: bf00 nop
armv7mthumb_fpv5#
00000000 <floordiv_float_float>:
0: eec0 7a20 vdiv.f32 s15, s0, s1
4: febb 0a67 vrintm.f32 s0, s15
8: f7ff bffe b.w 0 <result_float_float>
8: R_ARM_THM_JUMP24 result_float_float
armv7thumb#
00000000 <floordiv_float_float>:
0: ee80 0a20 vdiv.f32 s0, s0, s1
4: b508 push {r3, lr}
6: ed2d 8b02 vpush {d8}
a: eeb0 8a60 vmov.f32 s16, s1
e: f7ff fffe bl 0 <floordiv_float_float>
e: R_ARM_THM_CALL floorf
12: eef0 0a48 vmov.f32 s1, s16
16: ecbd 8b02 vpop {d8}
1a: e8bd 4008 ldmia.w sp!, {r3, lr}
1e: f7ff bffe b.w 0 <result_float_float>
1e: R_ARM_THM_JUMP24 result_float_float
22: bf00 nop
armv81mthumb#
00000000 <floordiv_float_float>:
0: eec0 7a20 vdiv.f32 s15, s0, s1
4: febb 0a67 vrintm.f32 s0, s15
8: f7ff bffe b.w 0 <result_float_float>
8: R_ARM_THM_JUMP24 result_float_float
riscv32#
00000000 <floordiv_float_float>:
0: 18b57553 fdiv.s fa0,fa0,fa1
4: 1101 addi sp,sp,-32
6: ce06 sw ra,28(sp)
8: e62e fsw fa1,12(sp)
a: 00000097 auipc ra,0x0
a: R_RISCV_CALL_PLT floorf
e: 000080e7 jalr ra # a <floordiv_float_float+0xa>
12: 65b2 flw fa1,12(sp)
14: 40f2 lw ra,28(sp)
16: 6105 addi sp,sp,32
18: 00000317 auipc t1,0x0
18: R_RISCV_CALL_PLT result_float_float
1c: 00030067 jr t1 # 18 <floordiv_float_float+0x18>
riscv64#
0000000000000000 <floordiv_float_float>:
0: 18b57553 fdiv.s fa0,fa0,fa1
4: 1101 addi sp,sp,-32
6: a422 fsd fs0,8(sp)
8: 20b58453 fmv.s fs0,fa1
c: ec06 sd ra,24(sp)
e: 00000097 auipc ra,0x0
e: R_RISCV_CALL_PLT floorf
12: 000080e7 jalr ra # e <floordiv_float_float+0xe>
16: 60e2 ld ra,24(sp)
18: 208405d3 fmv.s fa1,fs0
1c: 2422 fld fs0,8(sp)
1e: 6105 addi sp,sp,32
20: 00000317 auipc t1,0x0
20: R_RISCV_CALL_PLT result_float_float
24: 00030067 jr t1 # 20 <floordiv_float_float+0x20>
tricore#
00000000 <floordiv_float_float>:
0: 4b 54 51 40 div.f %d4,%d4,%d5
4: 02 58 mov %d8,%d5
6: 6d 00 00 00 call 6 <floordiv_float_float+0x6>
6: R_TRICORE_24REL floorf
a: 0b 28 10 48 mov %e4,%d8,%d2
e: 1d 00 00 00 j e <floordiv_float_float+0xe>
e: R_TRICORE_24REL result_float_float
x86#
00000000 <floordiv_float_float>:
0: 83 ec 1c sub $0x1c,%esp
3: d9 7c 24 0e fnstcw 0xe(%esp)
7: d9 44 24 24 flds 0x24(%esp)
b: d9 44 24 20 flds 0x20(%esp)
f: 0f b7 44 24 0e movzwl 0xe(%esp),%eax
14: d8 f1 fdiv %st(1),%st
16: 80 e4 f3 and $0xf3,%ah
19: 80 cc 04 or $0x4,%ah
1c: 66 89 44 24 0c mov %ax,0xc(%esp)
21: d9 6c 24 0c fldcw 0xc(%esp)
25: d9 fc frndint
27: d9 6c 24 0e fldcw 0xe(%esp)
2b: d9 c9 fxch %st(1)
2d: d9 5c 24 24 fstps 0x24(%esp)
31: d9 5c 24 20 fstps 0x20(%esp)
35: 83 c4 1c add $0x1c,%esp
38: e9 fc ff ff ff jmp 39 <floordiv_float_float+0x39>
39: R_386_PC32 result_float_float
x86_64#
0000000000000000 <floordiv_float_float>:
0: f3 0f 5e c1 divss %xmm1,%xmm0
4: f3 0f 10 1d 00 00 00 movss 0x0(%rip),%xmm3 # c <floordiv_float_float+0xc>
b: 00
8: R_X86_64_PC32 .LC16-0x4
c: f3 0f 10 25 00 00 00 movss 0x0(%rip),%xmm4 # 14 <floordiv_float_float+0x14>
13: 00
10: R_X86_64_PC32 .LC15-0x4
14: 0f 28 d0 movaps %xmm0,%xmm2
17: 0f 54 d3 andps %xmm3,%xmm2
1a: 0f 2e e2 ucomiss %xmm2,%xmm4
1d: 76 2c jbe 4b <floordiv_float_float+0x4b>
1f: f3 0f 2c c0 cvttss2si %xmm0,%eax
23: 66 0f ef d2 pxor %xmm2,%xmm2
27: f3 0f 10 2d 00 00 00 movss 0x0(%rip),%xmm5 # 2f <floordiv_float_float+0x2f>
2e: 00
2b: R_X86_64_PC32 .LC10-0x4
2f: 0f 55 d8 andnps %xmm0,%xmm3
32: f3 0f 2a d0 cvtsi2ss %eax,%xmm2
36: 0f 28 e2 movaps %xmm2,%xmm4
39: f3 0f c2 e0 06 cmpnless %xmm0,%xmm4
3e: 0f 54 e5 andps %xmm5,%xmm4
41: f3 0f 5c d4 subss %xmm4,%xmm2
45: 0f 56 d3 orps %xmm3,%xmm2
48: 0f 28 c2 movaps %xmm2,%xmm0
4b: e9 00 00 00 00 jmp 50 <.LC2>
4c: R_X86_64_PLT32 result_float_float-0x4
gt_int_int#
STENCIL void gt_int_int(int arg1, int arg2) {
result_int_int(arg1 > arg2, arg2);
}
arm64#
0000000000000000 <gt_int_int>:
0: 6b01001f cmp w0, w1
4: 1a9fd7e0 cset w0, gt
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <gt_int_int>:
0: e1500001 cmp r0, r1
4: d3a00000 movle r0, #0
8: c3a00001 movgt r0, #1
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7#
00000000 <gt_int_int>:
0: e1500001 cmp r0, r1
4: d3a00000 movle r0, #0
8: c3a00001 movgt r0, #1
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <gt_int_int>:
0: 4288 cmp r0, r1
2: bfd4 ite le
4: 2000 movle r0, #0
6: 2001 movgt r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <gt_int_int>:
0: 4288 cmp r0, r1
2: bfd4 ite le
4: 2000 movle r0, #0
6: 2001 movgt r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <gt_int_int>:
0: 4288 cmp r0, r1
2: bfd4 ite le
4: 2000 movle r0, #0
6: 2001 movgt r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <gt_int_int>:
0: 4288 cmp r0, r1
2: bfd4 ite le
4: 2000 movle r0, #0
6: 2001 movgt r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <gt_int_int>:
0: 00a5a533 slt a0,a1,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <gt_int_int+0x4>
riscv64#
0000000000000000 <gt_int_int>:
0: 00a5a533 slt a0,a1,a0
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <gt_int_int+0x4>
tricore#
00000000 <gt_int_int>:
0: 0b 45 20 41 lt %d4,%d5,%d4
4: 1d 00 00 00 j 4 <gt_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <gt_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 39 44 24 04 cmp %eax,0x4(%esp)
8: 0f 9f c0 setg %al
b: 0f b6 c0 movzbl %al,%eax
e: 89 44 24 04 mov %eax,0x4(%esp)
12: e9 fc ff ff ff jmp 13 <gt_int_int+0x13>
13: R_386_PC32 result_int_int
x86_64#
0000000000000000 <gt_int_int>:
0: 39 f7 cmp %esi,%edi
2: 40 0f 9f c7 setg %dil
6: 40 0f b6 ff movzbl %dil,%edi
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_int_int-0x4
gt_float_float#
STENCIL void gt_float_float(float arg1, float arg2) {
result_int_float(arg1 > arg2, arg2);
}
arm64#
0000000000000000 <gt_float_float>:
0: 1e212010 fcmpe s0, s1
4: 1e204020 fmov s0, s1
8: 1a9fd7e0 cset w0, gt
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <gt_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: c3a00001 movgt r0, #1
10: d3a00000 movle r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7#
00000000 <gt_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: c3a00001 movgt r0, #1
10: d3a00000 movle r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <gt_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bfcc ite gt
e: 2001 movgt r0, #1
10: 2000 movle r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7mthumb_fpv5#
00000000 <gt_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bfcc ite gt
e: 2001 movgt r0, #1
10: 2000 movle r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7thumb#
00000000 <gt_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bfcc ite gt
e: 2001 movgt r0, #1
10: 2000 movle r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv81mthumb#
00000000 <gt_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bfcc ite gt
e: 2001 movgt r0, #1
10: 2000 movle r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
riscv32#
00000000 <gt_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0f59553 flt.s a0,fa1,fa5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <gt_float_float+0xc>
riscv64#
0000000000000000 <gt_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0f59553 flt.s a0,fa1,fa5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <gt_float_float+0xc>
tricore#
00000000 <gt_float_float>:
0: 4b 54 01 40 cmp.f %d4,%d4,%d5
4: 37 04 61 41 extr.u %d4,%d4,2,1
8: 1d 00 00 00 j 8 <gt_float_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <gt_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: 31 c0 xor %eax,%eax
a: df f1 fcomip %st(1),%st
c: dd d8 fstp %st(0)
e: 0f 97 c0 seta %al
11: 89 44 24 04 mov %eax,0x4(%esp)
15: e9 fc ff ff ff jmp 16 <gt_float_float+0x16>
16: R_386_PC32 result_int_float
x86_64#
0000000000000000 <gt_float_float>:
0: 31 ff xor %edi,%edi
2: 0f 2f c1 comiss %xmm1,%xmm0
5: 0f 28 c1 movaps %xmm1,%xmm0
8: 40 0f 97 c7 seta %dil
c: e9 00 00 00 00 jmp 11 <.LC13+0x1>
d: R_X86_64_PLT32 result_int_float-0x4
ge_int_int#
STENCIL void ge_int_int(int arg1, int arg2) {
result_int_int(arg1 >= arg2, arg2);
}
arm64#
0000000000000000 <ge_int_int>:
0: 6b01001f cmp w0, w1
4: 1a9fb7e0 cset w0, ge // ge = tcont
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <ge_int_int>:
0: e1500001 cmp r0, r1
4: b3a00000 movlt r0, #0
8: a3a00001 movge r0, #1
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7#
00000000 <ge_int_int>:
0: e1500001 cmp r0, r1
4: b3a00000 movlt r0, #0
8: a3a00001 movge r0, #1
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <ge_int_int>:
0: 4288 cmp r0, r1
2: bfb4 ite lt
4: 2000 movlt r0, #0
6: 2001 movge r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <ge_int_int>:
0: 4288 cmp r0, r1
2: bfb4 ite lt
4: 2000 movlt r0, #0
6: 2001 movge r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <ge_int_int>:
0: 4288 cmp r0, r1
2: bfb4 ite lt
4: 2000 movlt r0, #0
6: 2001 movge r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <ge_int_int>:
0: 4288 cmp r0, r1
2: bfb4 ite lt
4: 2000 movlt r0, #0
6: 2001 movge r0, #1
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <ge_int_int>:
0: 00b52533 slt a0,a0,a1
4: 00154513 xori a0,a0,1
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <ge_int_int+0x8>
riscv64#
0000000000000000 <ge_int_int>:
0: 00b52533 slt a0,a0,a1
4: 00154513 xori a0,a0,1
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <ge_int_int+0x8>
tricore#
00000000 <ge_int_int>:
0: 0b 54 40 41 ge %d4,%d4,%d5
4: 1d 00 00 00 j 4 <ge_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <ge_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 39 44 24 04 cmp %eax,0x4(%esp)
8: 0f 9d c0 setge %al
b: 0f b6 c0 movzbl %al,%eax
e: 89 44 24 04 mov %eax,0x4(%esp)
12: e9 fc ff ff ff jmp 13 <ge_int_int+0x13>
13: R_386_PC32 result_int_int
x86_64#
0000000000000000 <ge_int_int>:
0: 39 f7 cmp %esi,%edi
2: 40 0f 9d c7 setge %dil
6: 40 0f b6 ff movzbl %dil,%edi
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_int_int-0x4
ge_float_float#
STENCIL void ge_float_float(float arg1, float arg2) {
result_int_float(arg1 >= arg2, arg2);
}
arm64#
0000000000000000 <ge_float_float>:
0: 1e212010 fcmpe s0, s1
4: 1e204020 fmov s0, s1
8: 1a9fb7e0 cset w0, ge // ge = tcont
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <ge_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: a3a00001 movge r0, #1
10: b3a00000 movlt r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7#
00000000 <ge_float_float>:
0: eeb40ae0 vcmpe.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: a3a00001 movge r0, #1
10: b3a00000 movlt r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <ge_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bfac ite ge
e: 2001 movge r0, #1
10: 2000 movlt r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7mthumb_fpv5#
00000000 <ge_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bfac ite ge
e: 2001 movge r0, #1
10: 2000 movlt r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7thumb#
00000000 <ge_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bfac ite ge
e: 2001 movge r0, #1
10: 2000 movlt r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv81mthumb#
00000000 <ge_float_float>:
0: eeb4 0ae0 vcmpe.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bfac ite ge
e: 2001 movge r0, #1
10: 2000 movlt r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
riscv32#
00000000 <ge_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0f58553 fle.s a0,fa1,fa5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <ge_float_float+0xc>
riscv64#
0000000000000000 <ge_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0f58553 fle.s a0,fa1,fa5
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <ge_float_float+0xc>
tricore#
00000000 <ge_float_float>:
0: 4b 54 01 40 cmp.f %d4,%d4,%d5
4: 87 44 a2 40 or.t %d4,%d4,2,%d4,1
8: 1d 00 00 00 j 8 <ge_float_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <ge_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: 31 c0 xor %eax,%eax
a: df f1 fcomip %st(1),%st
c: dd d8 fstp %st(0)
e: 0f 93 c0 setae %al
11: 89 44 24 04 mov %eax,0x4(%esp)
15: e9 fc ff ff ff jmp 16 <ge_float_float+0x16>
16: R_386_PC32 result_int_float
x86_64#
0000000000000000 <ge_float_float>:
0: 31 ff xor %edi,%edi
2: 0f 2f c1 comiss %xmm1,%xmm0
5: 0f 28 c1 movaps %xmm1,%xmm0
8: 40 0f 93 c7 setae %dil
c: e9 00 00 00 00 jmp 11 <.LC13+0x1>
d: R_X86_64_PLT32 result_int_float-0x4
eq_int_int#
STENCIL void eq_int_int(int arg1, int arg2) {
result_int_int(arg1 == arg2, arg2);
}
arm64#
0000000000000000 <eq_int_int>:
0: 6b01001f cmp w0, w1
4: 1a9f17e0 cset w0, eq // eq = none
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <eq_int_int>:
0: e0400001 sub r0, r0, r1
4: e16f0f10 clz r0, r0
8: e1a002a0 lsr r0, r0, #5
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7#
00000000 <eq_int_int>:
0: e0400001 sub r0, r0, r1
4: e16f0f10 clz r0, r0
8: e1a002a0 lsr r0, r0, #5
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <eq_int_int>:
0: 1a40 subs r0, r0, r1
2: fab0 f080 clz r0, r0
6: 0940 lsrs r0, r0, #5
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <eq_int_int>:
0: 1a40 subs r0, r0, r1
2: fab0 f080 clz r0, r0
6: 0940 lsrs r0, r0, #5
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <eq_int_int>:
0: 1a40 subs r0, r0, r1
2: fab0 f080 clz r0, r0
6: 0940 lsrs r0, r0, #5
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <eq_int_int>:
0: 1a40 subs r0, r0, r1
2: fab0 f080 clz r0, r0
6: 0940 lsrs r0, r0, #5
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <eq_int_int>:
0: 8d0d sub a0,a0,a1
2: 00153513 seqz a0,a0
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <eq_int_int+0x6>
riscv64#
0000000000000000 <eq_int_int>:
0: 8d0d sub a0,a0,a1
2: 00153513 seqz a0,a0
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <eq_int_int+0x6>
tricore#
00000000 <eq_int_int>:
0: 0b 54 00 41 eq %d4,%d4,%d5
4: 1d 00 00 00 j 4 <eq_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <eq_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 39 44 24 04 cmp %eax,0x4(%esp)
8: 0f 94 c0 sete %al
b: 0f b6 c0 movzbl %al,%eax
e: 89 44 24 04 mov %eax,0x4(%esp)
12: e9 fc ff ff ff jmp 13 <eq_int_int+0x13>
13: R_386_PC32 result_int_int
x86_64#
0000000000000000 <eq_int_int>:
0: 39 f7 cmp %esi,%edi
2: 40 0f 94 c7 sete %dil
6: 40 0f b6 ff movzbl %dil,%edi
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_int_int-0x4
eq_float_float#
STENCIL void eq_float_float(float arg1, float arg2) {
result_int_float(arg1 == arg2, arg2);
}
arm64#
0000000000000000 <eq_float_float>:
0: 1e212000 fcmp s0, s1
4: 1e204020 fmov s0, s1
8: 1a9f17e0 cset w0, eq // eq = none
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <eq_float_float>:
0: eeb40a60 vcmp.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: 03a00001 moveq r0, #1
10: 13a00000 movne r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7#
00000000 <eq_float_float>:
0: eeb40a60 vcmp.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: 03a00001 moveq r0, #1
10: 13a00000 movne r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <eq_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bf0c ite eq
e: 2001 moveq r0, #1
10: 2000 movne r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7mthumb_fpv5#
00000000 <eq_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bf0c ite eq
e: 2001 moveq r0, #1
10: 2000 movne r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7thumb#
00000000 <eq_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bf0c ite eq
e: 2001 moveq r0, #1
10: 2000 movne r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv81mthumb#
00000000 <eq_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bf0c ite eq
e: 2001 moveq r0, #1
10: 2000 movne r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
riscv32#
00000000 <eq_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0b7a553 feq.s a0,fa5,fa1
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <eq_float_float+0xc>
riscv64#
0000000000000000 <eq_float_float>:
0: 20a507d3 fmv.s fa5,fa0
4: 20b58553 fmv.s fa0,fa1
8: a0b7a553 feq.s a0,fa5,fa1
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <eq_float_float+0xc>
tricore#
00000000 <eq_float_float>:
0: 4b 54 01 40 cmp.f %d4,%d4,%d5
4: 37 04 e1 40 extr.u %d4,%d4,1,1
8: 1d 00 00 00 j 8 <eq_float_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <eq_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: 31 c0 xor %eax,%eax
a: ba 00 00 00 00 mov $0x0,%edx
f: df e9 fucomip %st(1),%st
11: dd d8 fstp %st(0)
13: 0f 9b c0 setnp %al
16: 0f 45 c2 cmovne %edx,%eax
19: 89 44 24 04 mov %eax,0x4(%esp)
1d: e9 fc ff ff ff jmp 1e <eq_float_float+0x1e>
1e: R_386_PC32 result_int_float
x86_64#
0000000000000000 <eq_float_float>:
0: 31 ff xor %edi,%edi
2: 0f 2e c1 ucomiss %xmm1,%xmm0
5: 0f 28 c1 movaps %xmm1,%xmm0
8: b8 00 00 00 00 mov $0x0,%eax
d: 40 0f 9b c7 setnp %dil
11: 0f 45 f8 cmovne %eax,%edi
14: e9 00 00 00 00 jmp 19 <.LC27+0x1>
15: R_X86_64_PLT32 result_int_float-0x4
ne_int_int#
STENCIL void ne_int_int(int arg1, int arg2) {
result_int_int(arg1 != arg2, arg2);
}
arm64#
0000000000000000 <ne_int_int>:
0: 6b01001f cmp w0, w1
4: 1a9f07e0 cset w0, ne // ne = any
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <ne_int_int>:
0: e0500001 subs r0, r0, r1
4: 13a00001 movne r0, #1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7#
00000000 <ne_int_int>:
0: e0500001 subs r0, r0, r1
4: 13a00001 movne r0, #1
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <ne_int_int>:
0: 1a40 subs r0, r0, r1
2: bf18 it ne
4: 2001 movne r0, #1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7mthumb_fpv5#
00000000 <ne_int_int>:
0: 1a40 subs r0, r0, r1
2: bf18 it ne
4: 2001 movne r0, #1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv7thumb#
00000000 <ne_int_int>:
0: 1a40 subs r0, r0, r1
2: bf18 it ne
4: 2001 movne r0, #1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
armv81mthumb#
00000000 <ne_int_int>:
0: 1a40 subs r0, r0, r1
2: bf18 it ne
4: 2001 movne r0, #1
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
riscv32#
00000000 <ne_int_int>:
0: 8d0d sub a0,a0,a1
2: 00a03533 snez a0,a0
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <ne_int_int+0x6>
riscv64#
0000000000000000 <ne_int_int>:
0: 8d0d sub a0,a0,a1
2: 00a03533 snez a0,a0
6: 00000317 auipc t1,0x0
6: R_RISCV_CALL_PLT result_int_int
a: 00030067 jr t1 # 6 <ne_int_int+0x6>
tricore#
00000000 <ne_int_int>:
0: 0b 54 10 41 ne %d4,%d4,%d5
4: 1d 00 00 00 j 4 <ne_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <ne_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 39 44 24 04 cmp %eax,0x4(%esp)
8: 0f 95 c0 setne %al
b: 0f b6 c0 movzbl %al,%eax
e: 89 44 24 04 mov %eax,0x4(%esp)
12: e9 fc ff ff ff jmp 13 <ne_int_int+0x13>
13: R_386_PC32 result_int_int
x86_64#
0000000000000000 <ne_int_int>:
0: 39 f7 cmp %esi,%edi
2: 40 0f 95 c7 setne %dil
6: 40 0f b6 ff movzbl %dil,%edi
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_int_int-0x4
ne_float_float#
STENCIL void ne_float_float(float arg1, float arg2) {
result_int_float(arg1 != arg2, arg2);
}
arm64#
0000000000000000 <ne_float_float>:
0: 1e212000 fcmp s0, s1
4: 1e204020 fmov s0, s1
8: 1a9f07e0 cset w0, ne // ne = any
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <ne_float_float>:
0: eeb40a60 vcmp.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: 13a00001 movne r0, #1
10: 03a00000 moveq r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7#
00000000 <ne_float_float>:
0: eeb40a60 vcmp.f32 s0, s1
4: eeb00a60 vmov.f32 s0, s1
8: eef1fa10 vmrs APSR_nzcv, fpscr
c: 13a00001 movne r0, #1
10: 03a00000 moveq r0, #0
14: eafffffe b 0 <result_int_float>
14: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <ne_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bf14 ite ne
e: 2001 movne r0, #1
10: 2000 moveq r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7mthumb_fpv5#
00000000 <ne_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bf14 ite ne
e: 2001 movne r0, #1
10: 2000 moveq r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv7thumb#
00000000 <ne_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eeb0 0a60 vmov.f32 s0, s1
8: eef1 fa10 vmrs APSR_nzcv, fpscr
c: bf14 ite ne
e: 2001 movne r0, #1
10: 2000 moveq r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
armv81mthumb#
00000000 <ne_float_float>:
0: eeb4 0a60 vcmp.f32 s0, s1
4: eef1 fa10 vmrs APSR_nzcv, fpscr
8: eeb0 0a60 vmov.f32 s0, s1
c: bf14 ite ne
e: 2001 movne r0, #1
10: 2000 moveq r0, #0
12: f7ff bffe b.w 0 <result_int_float>
12: R_ARM_THM_JUMP24 result_int_float
16: bf00 nop
riscv32#
00000000 <ne_float_float>:
0: a0b52553 feq.s a0,fa0,fa1
4: 20b58553 fmv.s fa0,fa1
8: 00154513 xori a0,a0,1
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <ne_float_float+0xc>
riscv64#
0000000000000000 <ne_float_float>:
0: a0b52553 feq.s a0,fa0,fa1
4: 20b58553 fmv.s fa0,fa1
8: 00154513 xori a0,a0,1
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <ne_float_float+0xc>
tricore#
00000000 <ne_float_float>:
0: 4b 54 01 40 cmp.f %d4,%d4,%d5
4: 8f d4 00 41 and %d4,%d4,13
8: 8b 04 20 42 ne %d4,%d4,0
c: 1d 00 00 00 j c <ne_float_float+0xc>
c: R_TRICORE_24REL result_int_float
x86#
00000000 <ne_float_float>:
0: d9 44 24 08 flds 0x8(%esp)
4: d9 44 24 04 flds 0x4(%esp)
8: 31 c0 xor %eax,%eax
a: ba 01 00 00 00 mov $0x1,%edx
f: df e9 fucomip %st(1),%st
11: dd d8 fstp %st(0)
13: 0f 9a c0 setp %al
16: 0f 45 c2 cmovne %edx,%eax
19: 89 44 24 04 mov %eax,0x4(%esp)
1d: e9 fc ff ff ff jmp 1e <ne_float_float+0x1e>
1e: R_386_PC32 result_int_float
x86_64#
0000000000000000 <ne_float_float>:
0: 31 ff xor %edi,%edi
2: 0f 2e c1 ucomiss %xmm1,%xmm0
5: 0f 28 c1 movaps %xmm1,%xmm0
8: b8 01 00 00 00 mov $0x1,%eax
d: 40 0f 9a c7 setp %dil
11: 0f 45 f8 cmovne %eax,%edi
14: e9 00 00 00 00 jmp 19 <.LC27+0x1>
15: R_X86_64_PLT32 result_int_float-0x4
bwand_int_int#
STENCIL void bwand_int_int(int arg1, int arg2) {
result_int_int(arg1 & arg2, arg2);
}
arm64#
0000000000000000 <bwand_int_int>:
0: 0a010000 and w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <bwand_int_int>:
0: e0000001 and r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <bwand_int_int>:
0: e0000001 and r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <bwand_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <bwand_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <bwand_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <bwand_int_int>:
0: 4008 ands r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <bwand_int_int>:
0: 8d6d and a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwand_int_int+0x2>
riscv64#
0000000000000000 <bwand_int_int>:
0: 8d6d and a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwand_int_int+0x2>
tricore#
00000000 <bwand_int_int>:
0: 26 54 and %d4,%d5
2: 1d 00 00 00 j 2 <bwand_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <bwand_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 21 44 24 04 and %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <bwand_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <bwand_int_int>:
0: 21 f7 and %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
bwor_int_int#
STENCIL void bwor_int_int(int arg1, int arg2) {
result_int_int(arg1 | arg2, arg2);
}
arm64#
0000000000000000 <bwor_int_int>:
0: 2a010000 orr w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <bwor_int_int>:
0: e1800001 orr r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <bwor_int_int>:
0: e1800001 orr r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <bwor_int_int>:
0: 4308 orrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <bwor_int_int>:
0: 4308 orrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <bwor_int_int>:
0: 4308 orrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <bwor_int_int>:
0: 4308 orrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <bwor_int_int>:
0: 8d4d or a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwor_int_int+0x2>
riscv64#
0000000000000000 <bwor_int_int>:
0: 8d4d or a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwor_int_int+0x2>
tricore#
00000000 <bwor_int_int>:
0: a6 54 or %d4,%d5
2: 1d 00 00 00 j 2 <bwor_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <bwor_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 09 44 24 04 or %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <bwor_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <bwor_int_int>:
0: 09 f7 or %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
bwxor_int_int#
STENCIL void bwxor_int_int(int arg1, int arg2) {
result_int_int(arg1 ^ arg2, arg2);
}
arm64#
0000000000000000 <bwxor_int_int>:
0: 4a010000 eor w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <bwxor_int_int>:
0: e0200001 eor r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <bwxor_int_int>:
0: e0200001 eor r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <bwxor_int_int>:
0: 4048 eors r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <bwxor_int_int>:
0: 4048 eors r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <bwxor_int_int>:
0: 4048 eors r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <bwxor_int_int>:
0: 4048 eors r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <bwxor_int_int>:
0: 8d2d xor a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwxor_int_int+0x2>
riscv64#
0000000000000000 <bwxor_int_int>:
0: 8d2d xor a0,a0,a1
2: 00000317 auipc t1,0x0
2: R_RISCV_CALL_PLT result_int_int
6: 00030067 jr t1 # 2 <bwxor_int_int+0x2>
tricore#
00000000 <bwxor_int_int>:
0: c6 54 xor %d4,%d5
2: 1d 00 00 00 j 2 <bwxor_int_int+0x2>
2: R_TRICORE_24REL result_int_int
x86#
00000000 <bwxor_int_int>:
0: 8b 44 24 08 mov 0x8(%esp),%eax
4: 31 44 24 04 xor %eax,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <bwxor_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <bwxor_int_int>:
0: 31 f7 xor %esi,%edi
2: e9 00 00 00 00 jmp 7 <.LC1+0x3>
3: R_X86_64_PLT32 result_int_int-0x4
lshift_int_int#
STENCIL void lshift_int_int(int arg1, int arg2) {
result_int_int(arg1 << arg2, arg2);
}
arm64#
0000000000000000 <lshift_int_int>:
0: 1ac12000 lsl w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <lshift_int_int>:
0: e1a00110 lsl r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <lshift_int_int>:
0: e1a00110 lsl r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <lshift_int_int>:
0: 4088 lsls r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <lshift_int_int>:
0: 4088 lsls r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <lshift_int_int>:
0: 4088 lsls r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <lshift_int_int>:
0: 4088 lsls r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <lshift_int_int>:
0: 00b51533 sll a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <lshift_int_int+0x4>
riscv64#
0000000000000000 <lshift_int_int>:
0: 00b5153b sllw a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <lshift_int_int+0x4>
tricore#
00000000 <lshift_int_int>:
0: 0f 54 00 40 sh %d4,%d4,%d5
4: 1d 00 00 00 j 4 <lshift_int_int+0x4>
4: R_TRICORE_24REL result_int_int
x86#
00000000 <lshift_int_int>:
0: 8b 4c 24 08 mov 0x8(%esp),%ecx
4: d3 64 24 04 shll %cl,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <lshift_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <lshift_int_int>:
0: 89 f1 mov %esi,%ecx
2: d3 e7 shl %cl,%edi
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_int_int-0x4
rshift_int_int#
STENCIL void rshift_int_int(int arg1, int arg2) {
result_int_int(arg1 >> arg2, arg2);
}
arm64#
0000000000000000 <rshift_int_int>:
0: 1ac12800 asr w0, w0, w1
4: 14000000 b 0 <result_int_int>
4: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <rshift_int_int>:
0: e1a00150 asr r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7#
00000000 <rshift_int_int>:
0: e1a00150 asr r0, r0, r1
4: eafffffe b 0 <result_int_int>
4: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <rshift_int_int>:
0: 4108 asrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7mthumb_fpv5#
00000000 <rshift_int_int>:
0: 4108 asrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv7thumb#
00000000 <rshift_int_int>:
0: 4108 asrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
armv81mthumb#
00000000 <rshift_int_int>:
0: 4108 asrs r0, r1
2: f7ff bffe b.w 0 <result_int_int>
2: R_ARM_THM_JUMP24 result_int_int
6: bf00 nop
riscv32#
00000000 <rshift_int_int>:
0: 40b55533 sra a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <rshift_int_int+0x4>
riscv64#
0000000000000000 <rshift_int_int>:
0: 40b5553b sraw a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <rshift_int_int+0x4>
tricore#
00000000 <rshift_int_int>:
0: 02 42 mov %d2,%d4
2: 8b 05 00 41 rsub %d4,%d5,0
6: 0f 42 20 40 shas %d4,%d2,%d4
a: 1d 00 00 00 j a <rshift_int_int+0xa>
a: R_TRICORE_24REL result_int_int
x86#
00000000 <rshift_int_int>:
0: 8b 4c 24 08 mov 0x8(%esp),%ecx
4: d3 7c 24 04 sarl %cl,0x4(%esp)
8: e9 fc ff ff ff jmp 9 <rshift_int_int+0x9>
9: R_386_PC32 result_int_int
x86_64#
0000000000000000 <rshift_int_int>:
0: 89 f1 mov %esi,%ecx
2: d3 ff sar %cl,%edi
4: e9 00 00 00 00 jmp 9 <.LC2+0x1>
5: R_X86_64_PLT32 result_int_int-0x4
mod_int_int#
STENCIL void mod_int_int(int arg1, int arg2) {
result_int_int(arg1 % arg2, arg2);
}
arm64#
0000000000000000 <mod_int_int>:
0: 1ac10c02 sdiv w2, w0, w1
4: 1b018040 msub w0, w2, w1, w0
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <mod_int_int>:
0: e92d4010 push {r4, lr}
4: e1a04001 mov r4, r1
8: ebfffffe bl 128 <__aeabi_idivmod>
8: R_ARM_CALL __aeabi_idivmod
c: e1a00001 mov r0, r1
10: e1a01004 mov r1, r4
14: e8bd4010 pop {r4, lr}
18: eafffffe b 0 <result_int_int>
18: R_ARM_JUMP24 result_int_int
armv7#
00000000 <mod_int_int>:
0: e92d4010 push {r4, lr}
4: e1a04001 mov r4, r1
8: ebfffffe bl 128 <__aeabi_idivmod>
8: R_ARM_CALL __aeabi_idivmod
c: e1a00001 mov r0, r1
10: e1a01004 mov r1, r4
14: e8bd4010 pop {r4, lr}
18: eafffffe b 0 <result_int_int>
18: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <mod_int_int>:
0: fb90 f3f1 sdiv r3, r0, r1
4: fb03 0011 mls r0, r3, r1, r0
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7mthumb_fpv5#
00000000 <mod_int_int>:
0: fb90 f3f1 sdiv r3, r0, r1
4: fb03 0011 mls r0, r3, r1, r0
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
armv7thumb#
00000000 <mod_int_int>:
0: b510 push {r4, lr}
2: 460c mov r4, r1
4: f7ff fffe bl 294 <__aeabi_idivmod>
4: R_ARM_THM_CALL __aeabi_idivmod
8: 4608 mov r0, r1
a: 4621 mov r1, r4
c: e8bd 4010 ldmia.w sp!, {r4, lr}
10: f7ff bffe b.w 0 <result_int_int>
10: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <mod_int_int>:
0: fb90 f3f1 sdiv r3, r0, r1
4: fb03 0011 mls r0, r3, r1, r0
8: f7ff bffe b.w 0 <result_int_int>
8: R_ARM_THM_JUMP24 result_int_int
riscv32#
00000000 <mod_int_int>:
0: 02b56533 rem a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <mod_int_int+0x4>
riscv64#
0000000000000000 <mod_int_int>:
0: 02b5653b remw a0,a0,a1
4: 00000317 auipc t1,0x0
4: R_RISCV_CALL_PLT result_int_int
8: 00030067 jr t1 # 4 <mod_int_int+0x4>
tricore#
00000000 <mod_int_int>:
0: 4b 54 01 22 div %e2,%d4,%d5
4: 02 34 mov %d4,%d3
6: 1d 00 00 00 j 6 <mod_int_int+0x6>
6: R_TRICORE_24REL result_int_int
x86#
00000000 <mod_int_int>:
0: 8b 44 24 04 mov 0x4(%esp),%eax
4: 8b 4c 24 08 mov 0x8(%esp),%ecx
8: 99 cltd
9: f7 f9 idiv %ecx
b: 89 54 24 04 mov %edx,0x4(%esp)
f: e9 fc ff ff ff jmp 10 <mod_int_int+0x10>
10: R_386_PC32 result_int_int
x86_64#
0000000000000000 <mod_int_int>:
0: 89 f8 mov %edi,%eax
2: 99 cltd
3: f7 fe idiv %esi
5: 89 d7 mov %edx,%edi
7: e9 00 00 00 00 jmp c <.LC3>
8: R_X86_64_PLT32 result_int_int-0x4