Load and store stencils#
load_int_reg0_int_int#
STENCIL void load_int_reg0_int_int(int arg1, int arg2) {
result_int_int(dummy_int, arg2);
}
arm64#
0000000000000000 <load_int_reg0_int_int>:
0: 90000000 adrp x0, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400000 ldr w0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <load_int_reg0_int_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg0_int_int+0xc>
4: e5930000 ldr r0, [r3]
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg0_int_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <load_int_reg0_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg0_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg0_int_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6818 ldr r0, [r3, #0]
a: f7ff bffe b.w 0 <result_int_int>
a: R_ARM_THM_JUMP24 result_int_int
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg0_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg0_int_int>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg0_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg0_int_int+0x8>
riscv64#
0000000000000000 <load_int_reg0_int_int>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg0_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg0_int_int+0x8>
tricore#
00000000 <load_int_reg0_int_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <load_int_reg0_int_int>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg0_int_int+0x8>
8: R_TRICORE_24REL result_int_int
x86#
00000000 <load_int_reg0_int_int>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 04 mov %eax,0x4(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg0_int_int+0xa>
a: R_386_PC32 result_int_int
x86_64#
0000000000000000 <load_int_reg0_int_int>:
0: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 6 <load_int_reg0_int_int+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_int-0x4
load_int_reg1_int_int#
STENCIL void load_int_reg1_int_int(int arg1, int arg2) {
result_int_int(arg1, dummy_int);
}
arm64#
0000000000000000 <load_int_reg1_int_int>:
0: 90000001 adrp x1, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400021 ldr w1, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <load_int_reg1_int_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg1_int_int+0xc>
4: e5931000 ldr r1, [r3]
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg1_int_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5931000 ldr r1, [r3]
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <load_int_reg1_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_int+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg1_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_int+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg1_int_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6819 ldr r1, [r3, #0]
a: f7ff bffe b.w 0 <result_int_int>
a: R_ARM_THM_JUMP24 result_int_int
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg1_int_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_int+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg1_int_int>:
0: 00000597 auipc a1,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 0005a583 lw a1,0(a1) # 0 <load_int_reg1_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg1_int_int+0x8>
riscv64#
0000000000000000 <load_int_reg1_int_int>:
0: 00000597 auipc a1,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 0005a583 lw a1,0(a1) # 0 <load_int_reg1_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg1_int_int+0x8>
tricore#
00000000 <load_int_reg1_int_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <load_int_reg1_int_int>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg1_int_int+0x8>
8: R_TRICORE_24REL result_int_int
x86#
00000000 <load_int_reg1_int_int>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 08 mov %eax,0x8(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg1_int_int+0xa>
a: R_386_PC32 result_int_int
x86_64#
0000000000000000 <load_int_reg1_int_int>:
0: 8b 35 00 00 00 00 mov 0x0(%rip),%esi # 6 <load_int_reg1_int_int+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_int-0x4
load_float_reg0_int_int#
STENCIL void load_float_reg0_int_int(int arg1, int arg2) {
result_float_int(dummy_float, arg2);
}
arm64#
0000000000000000 <load_float_reg0_int_int>:
0: 90000002 adrp x2, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: 2a0103e0 mov w0, w1
8: bd400040 ldr s0, [x2]
8: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
c: 14000000 b 0 <result_float_int>
c: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <load_float_reg0_int_int>:
0: e59f3008 ldr r3, [pc, #8] @ 10 <load_float_reg0_int_int+0x10>
4: e1a00001 mov r0, r1
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg0_int_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: e1a00001 mov r0, r1
c: ed930a00 vldr s0, [r3]
10: eafffffe b 0 <result_float_int>
10: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <load_float_reg0_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_int_int+0xc>)
2: 4608 mov r0, r1
4: ed93 0a00 vldr s0, [r3]
8: f7ff bffe b.w 0 <result_float_int>
8: R_ARM_THM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg0_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_int_int+0xc>)
2: 4608 mov r0, r1
4: ed93 0a00 vldr s0, [r3]
8: f7ff bffe b.w 0 <result_float_int>
8: R_ARM_THM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg0_int_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: 4608 mov r0, r1
a: ed93 0a00 vldr s0, [r3]
e: f7ff bffe b.w 0 <result_float_int>
e: R_ARM_THM_JUMP24 result_float_int
12: bf00 nop
armv81mthumb#
00000000 <load_float_reg0_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_int_int+0xc>)
2: 4608 mov r0, r1
4: ed93 0a00 vldr s0, [r3]
8: f7ff bffe b.w 0 <result_float_int>
8: R_ARM_THM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg0_int_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg0_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 852e mv a0,a1
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_int
e: 00030067 jr t1 # a <load_float_reg0_int_int+0xa>
riscv64#
0000000000000000 <load_float_reg0_int_int>:
0: 852e mv a0,a1
2: 00000797 auipc a5,0x0
2: R_RISCV_PCREL_HI20 dummy_float
6: 0007a507 flw fa0,0(a5) # 2 <load_float_reg0_int_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_int
e: 00030067 jr t1 # a <load_float_reg0_int_int+0xa>
tricore#
00000000 <load_float_reg0_int_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg0_int_int>>
4: R_TRICORE_LO2 dummy_float
8: 54 24 ld.w %d4,[%a2]
a: 1d 00 00 00 j a <load_float_reg0_int_int+0xa>
a: R_TRICORE_24REL result_float_int
x86#
00000000 <load_float_reg0_int_int>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg0_int_int+0xb>
b: R_386_PC32 result_float_int
x86_64#
0000000000000000 <load_float_reg0_int_int>:
0: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # 8 <load_float_reg0_int_int+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: 89 f7 mov %esi,%edi
a: e9 00 00 00 00 jmp f <.LC3+0x3>
b: R_X86_64_PLT32 result_float_int-0x4
load_float_reg1_int_int#
STENCIL void load_float_reg1_int_int(int arg1, int arg2) {
result_int_float(arg1, dummy_float);
}
arm64#
0000000000000000 <load_float_reg1_int_int>:
0: 90000001 adrp x1, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400020 ldr s0, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_int_float>
8: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <load_float_reg1_int_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg1_int_int+0xc>
4: ed930a00 vldr s0, [r3]
8: eafffffe b 0 <result_int_float>
8: R_ARM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg1_int_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_int_float>
c: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <load_float_reg1_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg1_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg1_int_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed93 0a00 vldr s0, [r3]
c: f7ff bffe b.w 0 <result_int_float>
c: R_ARM_THM_JUMP24 result_int_float
armv81mthumb#
00000000 <load_float_reg1_int_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg1_int_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg1_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_float_reg1_int_int+0x8>
riscv64#
0000000000000000 <load_float_reg1_int_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg1_int_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_float_reg1_int_int+0x8>
tricore#
00000000 <load_float_reg1_int_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg1_int_int>>
4: R_TRICORE_LO2 dummy_float
8: 54 25 ld.w %d5,[%a2]
a: 1d 00 00 00 j a <load_float_reg1_int_int+0xa>
a: R_TRICORE_24REL result_int_float
x86#
00000000 <load_float_reg1_int_int>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 08 fstps 0x8(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg1_int_int+0xb>
b: R_386_PC32 result_int_float
x86_64#
0000000000000000 <load_float_reg1_int_int>:
0: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # 8 <load_float_reg1_int_int+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_int_float-0x4
load_int_reg0_int_float#
STENCIL void load_int_reg0_int_float(int arg1, float arg2) {
result_int_float(dummy_int, arg2);
}
arm64#
0000000000000000 <load_int_reg0_int_float>:
0: 90000000 adrp x0, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400000 ldr w0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_float>
8: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <load_int_reg0_int_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg0_int_float+0xc>
4: e5930000 ldr r0, [r3]
8: eafffffe b 0 <result_int_float>
8: R_ARM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg0_int_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_int_float>
c: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <load_int_reg0_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg0_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg0_int_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6818 ldr r0, [r3, #0]
a: f7ff bffe b.w 0 <result_int_float>
a: R_ARM_THM_JUMP24 result_int_float
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg0_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg0_int_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg0_int_float>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg0_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_int_reg0_int_float+0x8>
riscv64#
0000000000000000 <load_int_reg0_int_float>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg0_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_int_reg0_int_float+0x8>
tricore#
00000000 <load_int_reg0_int_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <load_int_reg0_int_float>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg0_int_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <load_int_reg0_int_float>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 04 mov %eax,0x4(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg0_int_float+0xa>
a: R_386_PC32 result_int_float
x86_64#
0000000000000000 <load_int_reg0_int_float>:
0: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 6 <load_int_reg0_int_float+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_float-0x4
load_int_reg1_int_float#
STENCIL void load_int_reg1_int_float(int arg1, float arg2) {
result_int_int(arg1, dummy_int);
}
arm64#
0000000000000000 <load_int_reg1_int_float>:
0: 90000001 adrp x1, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400021 ldr w1, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <load_int_reg1_int_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg1_int_float+0xc>
4: e5931000 ldr r1, [r3]
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg1_int_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5931000 ldr r1, [r3]
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <load_int_reg1_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_float+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg1_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_float+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg1_int_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6819 ldr r1, [r3, #0]
a: f7ff bffe b.w 0 <result_int_int>
a: R_ARM_THM_JUMP24 result_int_int
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg1_int_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_int_float+0x8>)
2: 6819 ldr r1, [r3, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg1_int_float>:
0: 00000597 auipc a1,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 0005a583 lw a1,0(a1) # 0 <load_int_reg1_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg1_int_float+0x8>
riscv64#
0000000000000000 <load_int_reg1_int_float>:
0: 00000597 auipc a1,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 0005a583 lw a1,0(a1) # 0 <load_int_reg1_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <load_int_reg1_int_float+0x8>
tricore#
00000000 <load_int_reg1_int_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <load_int_reg1_int_float>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg1_int_float+0x8>
8: R_TRICORE_24REL result_int_int
x86#
00000000 <load_int_reg1_int_float>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 08 mov %eax,0x8(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg1_int_float+0xa>
a: R_386_PC32 result_int_int
x86_64#
0000000000000000 <load_int_reg1_int_float>:
0: 8b 35 00 00 00 00 mov 0x0(%rip),%esi # 6 <load_int_reg1_int_float+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_int-0x4
load_float_reg0_int_float#
STENCIL void load_float_reg0_int_float(int arg1, float arg2) {
result_float_float(dummy_float, arg2);
}
arm64#
0000000000000000 <load_float_reg0_int_float>:
0: 90000000 adrp x0, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: 1e204001 fmov s1, s0
8: bd400000 ldr s0, [x0]
8: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
c: 14000000 b 0 <result_float_float>
c: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <load_float_reg0_int_float>:
0: e59f3008 ldr r3, [pc, #8] @ 10 <load_float_reg0_int_float+0x10>
4: eef00a40 vmov.f32 s1, s0
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg0_int_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: eef00a40 vmov.f32 s1, s0
c: ed930a00 vldr s0, [r3]
10: eafffffe b 0 <result_float_float>
10: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <load_float_reg0_int_float>:
0: 4b03 ldr r3, [pc, #12] @ (10 <load_float_reg0_int_float+0x10>)
2: eef0 0a40 vmov.f32 s1, s0
6: ed93 0a00 vldr s0, [r3]
a: f7ff bffe b.w 0 <result_float_float>
a: R_ARM_THM_JUMP24 result_float_float
e: bf00 nop
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg0_int_float>:
0: 4b03 ldr r3, [pc, #12] @ (10 <load_float_reg0_int_float+0x10>)
2: eef0 0a40 vmov.f32 s1, s0
6: ed93 0a00 vldr s0, [r3]
a: f7ff bffe b.w 0 <result_float_float>
a: R_ARM_THM_JUMP24 result_float_float
e: bf00 nop
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg0_int_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: eef0 0a40 vmov.f32 s1, s0
c: ed93 0a00 vldr s0, [r3]
10: f7ff bffe b.w 0 <result_float_float>
10: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <load_float_reg0_int_float>:
0: 4b03 ldr r3, [pc, #12] @ (10 <load_float_reg0_int_float+0x10>)
2: eef0 0a40 vmov.f32 s1, s0
6: ed93 0a00 vldr s0, [r3]
a: f7ff bffe b.w 0 <result_float_float>
a: R_ARM_THM_JUMP24 result_float_float
e: bf00 nop
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg0_int_float>:
0: 20a505d3 fmv.s fa1,fa0
4: 00000797 auipc a5,0x0
4: R_RISCV_PCREL_HI20 dummy_float
8: 0007a507 flw fa0,0(a5) # 4 <load_float_reg0_int_float+0x4>
8: R_RISCV_PCREL_LO12_I .L0
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_float_float
10: 00030067 jr t1 # c <load_float_reg0_int_float+0xc>
riscv64#
0000000000000000 <load_float_reg0_int_float>:
0: 20a505d3 fmv.s fa1,fa0
4: 00000797 auipc a5,0x0
4: R_RISCV_PCREL_HI20 dummy_float
8: 0007a507 flw fa0,0(a5) # 4 <load_float_reg0_int_float+0x4>
8: R_RISCV_PCREL_LO12_I .L0
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_float_float
10: 00030067 jr t1 # c <load_float_reg0_int_float+0xc>
tricore#
00000000 <load_float_reg0_int_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg0_int_float>>
4: R_TRICORE_LO2 dummy_float
8: 54 24 ld.w %d4,[%a2]
a: 1d 00 00 00 j a <load_float_reg0_int_float+0xa>
a: R_TRICORE_24REL result_float_float
x86#
00000000 <load_float_reg0_int_float>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg0_int_float+0xb>
b: R_386_PC32 result_float_float
x86_64#
0000000000000000 <load_float_reg0_int_float>:
0: 0f 28 c8 movaps %xmm0,%xmm1
3: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # b <load_float_reg0_int_float+0xb>
a: 00
7: R_X86_64_PC32 dummy_float-0x4
b: e9 00 00 00 00 jmp 10 <.LC13>
c: R_X86_64_PLT32 result_float_float-0x4
load_float_reg1_int_float#
STENCIL void load_float_reg1_int_float(int arg1, float arg2) {
result_int_float(arg1, dummy_float);
}
arm64#
0000000000000000 <load_float_reg1_int_float>:
0: 90000001 adrp x1, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400020 ldr s0, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_int_float>
8: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <load_float_reg1_int_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg1_int_float+0xc>
4: ed930a00 vldr s0, [r3]
8: eafffffe b 0 <result_int_float>
8: R_ARM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg1_int_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_int_float>
c: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <load_float_reg1_int_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg1_int_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg1_int_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed93 0a00 vldr s0, [r3]
c: f7ff bffe b.w 0 <result_int_float>
c: R_ARM_THM_JUMP24 result_int_float
armv81mthumb#
00000000 <load_float_reg1_int_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_int_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_int_float>
6: R_ARM_THM_JUMP24 result_int_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg1_int_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg1_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_float_reg1_int_float+0x8>
riscv64#
0000000000000000 <load_float_reg1_int_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg1_int_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <load_float_reg1_int_float+0x8>
tricore#
00000000 <load_float_reg1_int_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg1_int_float>>
4: R_TRICORE_LO2 dummy_float
8: 54 25 ld.w %d5,[%a2]
a: 1d 00 00 00 j a <load_float_reg1_int_float+0xa>
a: R_TRICORE_24REL result_int_float
x86#
00000000 <load_float_reg1_int_float>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 08 fstps 0x8(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg1_int_float+0xb>
b: R_386_PC32 result_int_float
x86_64#
0000000000000000 <load_float_reg1_int_float>:
0: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # 8 <load_float_reg1_int_float+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_int_float-0x4
load_int_reg0_float_int#
STENCIL void load_int_reg0_float_int(float arg1, int arg2) {
result_int_int(dummy_int, arg2);
}
arm64#
0000000000000000 <load_int_reg0_float_int>:
0: 90000002 adrp x2, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: 2a0003e1 mov w1, w0
8: b9400040 ldr w0, [x2]
8: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
c: 14000000 b 0 <result_int_int>
c: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <load_int_reg0_float_int>:
0: e59f3008 ldr r3, [pc, #8] @ 10 <load_int_reg0_float_int+0x10>
4: e1a01000 mov r1, r0
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg0_float_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e1a01000 mov r1, r0
c: e5930000 ldr r0, [r3]
10: eafffffe b 0 <result_int_int>
10: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <load_int_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_int+0xc>)
2: 4601 mov r1, r0
4: 6818 ldr r0, [r3, #0]
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_int+0xc>)
2: 4601 mov r1, r0
4: 6818 ldr r0, [r3, #0]
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg0_float_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 4601 mov r1, r0
a: 6818 ldr r0, [r3, #0]
c: f7ff bffe b.w 0 <result_int_int>
c: R_ARM_THM_JUMP24 result_int_int
armv81mthumb#
00000000 <load_int_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_int+0xc>)
2: 4601 mov r1, r0
4: 6818 ldr r0, [r3, #0]
6: f7ff bffe b.w 0 <result_int_int>
6: R_ARM_THM_JUMP24 result_int_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg0_float_int>:
0: 85aa mv a1,a0
2: 00000517 auipc a0,0x0
2: R_RISCV_PCREL_HI20 dummy_int
6: 00052503 lw a0,0(a0) # 2 <load_int_reg0_float_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_int_int
e: 00030067 jr t1 # a <load_int_reg0_float_int+0xa>
riscv64#
0000000000000000 <load_int_reg0_float_int>:
0: 85aa mv a1,a0
2: 00000517 auipc a0,0x0
2: R_RISCV_PCREL_HI20 dummy_int
6: 00052503 lw a0,0(a0) # 2 <load_int_reg0_float_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_int_int
e: 00030067 jr t1 # a <load_int_reg0_float_int+0xa>
tricore#
00000000 <load_int_reg0_float_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <load_int_reg0_float_int>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg0_float_int+0x8>
8: R_TRICORE_24REL result_int_int
x86#
00000000 <load_int_reg0_float_int>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 04 mov %eax,0x4(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg0_float_int+0xa>
a: R_386_PC32 result_int_int
x86_64#
0000000000000000 <load_int_reg0_float_int>:
0: 89 fe mov %edi,%esi
2: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 8 <load_int_reg0_float_int+0x8>
4: R_X86_64_PC32 dummy_int-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_int_int-0x4
load_int_reg1_float_int#
STENCIL void load_int_reg1_float_int(float arg1, int arg2) {
result_float_int(arg1, dummy_int);
}
arm64#
0000000000000000 <load_int_reg1_float_int>:
0: 90000000 adrp x0, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400000 ldr w0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <load_int_reg1_float_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg1_float_int+0xc>
4: e5930000 ldr r0, [r3]
8: eafffffe b 0 <result_float_int>
8: R_ARM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg1_float_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <load_int_reg1_float_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg1_float_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg1_float_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6818 ldr r0, [r3, #0]
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg1_float_int>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_int+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg1_float_int>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg1_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_int_reg1_float_int+0x8>
riscv64#
0000000000000000 <load_int_reg1_float_int>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg1_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_int_reg1_float_int+0x8>
tricore#
00000000 <load_int_reg1_float_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <load_int_reg1_float_int>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg1_float_int+0x8>
8: R_TRICORE_24REL result_float_int
x86#
00000000 <load_int_reg1_float_int>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 08 mov %eax,0x8(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg1_float_int+0xa>
a: R_386_PC32 result_float_int
x86_64#
0000000000000000 <load_int_reg1_float_int>:
0: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 6 <load_int_reg1_float_int+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_float_int-0x4
load_float_reg0_float_int#
STENCIL void load_float_reg0_float_int(float arg1, int arg2) {
result_float_int(dummy_float, arg2);
}
arm64#
0000000000000000 <load_float_reg0_float_int>:
0: 90000001 adrp x1, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400020 ldr s0, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <load_float_reg0_float_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg0_float_int+0xc>
4: ed930a00 vldr s0, [r3]
8: eafffffe b 0 <result_float_int>
8: R_ARM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg0_float_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <load_float_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg0_float_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed93 0a00 vldr s0, [r3]
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
armv81mthumb#
00000000 <load_float_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_int+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg0_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg0_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_float_reg0_float_int+0x8>
riscv64#
0000000000000000 <load_float_reg0_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg0_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_float_reg0_float_int+0x8>
tricore#
00000000 <load_float_reg0_float_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg0_float_int>>
4: R_TRICORE_LO2 dummy_float
8: 54 24 ld.w %d4,[%a2]
a: 1d 00 00 00 j a <load_float_reg0_float_int+0xa>
a: R_TRICORE_24REL result_float_int
x86#
00000000 <load_float_reg0_float_int>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg0_float_int+0xb>
b: R_386_PC32 result_float_int
x86_64#
0000000000000000 <load_float_reg0_float_int>:
0: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # 8 <load_float_reg0_float_int+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_int-0x4
load_float_reg1_float_int#
STENCIL void load_float_reg1_float_int(float arg1, int arg2) {
result_float_float(arg1, dummy_float);
}
arm64#
0000000000000000 <load_float_reg1_float_int>:
0: 90000000 adrp x0, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400001 ldr s1, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <load_float_reg1_float_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg1_float_int+0xc>
4: edd30a00 vldr s1, [r3]
8: eafffffe b 0 <result_float_float>
8: R_ARM_JUMP24 result_float_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg1_float_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: edd30a00 vldr s1, [r3]
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <load_float_reg1_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_int+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg1_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_int+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg1_float_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: edd3 0a00 vldr s1, [r3]
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <load_float_reg1_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_int+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg1_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a587 flw fa1,0(a5) # 0 <load_float_reg1_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg1_float_int+0x8>
riscv64#
0000000000000000 <load_float_reg1_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a587 flw fa1,0(a5) # 0 <load_float_reg1_float_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg1_float_int+0x8>
tricore#
00000000 <load_float_reg1_float_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg1_float_int>>
4: R_TRICORE_LO2 dummy_float
8: 54 25 ld.w %d5,[%a2]
a: 1d 00 00 00 j a <load_float_reg1_float_int+0xa>
a: R_TRICORE_24REL result_float_float
x86#
00000000 <load_float_reg1_float_int>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 08 fstps 0x8(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg1_float_int+0xb>
b: R_386_PC32 result_float_float
x86_64#
0000000000000000 <load_float_reg1_float_int>:
0: f3 0f 10 0d 00 00 00 movss 0x0(%rip),%xmm1 # 8 <load_float_reg1_float_int+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_float-0x4
load_int_reg0_float_float#
STENCIL void load_int_reg0_float_float(float arg1, float arg2) {
result_int_float(dummy_int, arg2);
}
arm64#
0000000000000000 <load_int_reg0_float_float>:
0: 90000000 adrp x0, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: 1e204020 fmov s0, s1
8: b9400000 ldr w0, [x0]
8: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
c: 14000000 b 0 <result_int_float>
c: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <load_int_reg0_float_float>:
0: e59f3008 ldr r3, [pc, #8] @ 10 <load_int_reg0_float_float+0x10>
4: eeb00a60 vmov.f32 s0, s1
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_int_float>
c: R_ARM_JUMP24 result_int_float
10: 00000000 .word 0x00000000
10: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg0_float_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: eeb00a60 vmov.f32 s0, s1
c: e5930000 ldr r0, [r3]
10: eafffffe b 0 <result_int_float>
10: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <load_int_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_float+0xc>)
2: eeb0 0a60 vmov.f32 s0, s1
6: 6818 ldr r0, [r3, #0]
8: f7ff bffe b.w 0 <result_int_float>
8: R_ARM_THM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_float+0xc>)
2: eeb0 0a60 vmov.f32 s0, s1
6: 6818 ldr r0, [r3, #0]
8: f7ff bffe b.w 0 <result_int_float>
8: R_ARM_THM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg0_float_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: eeb0 0a60 vmov.f32 s0, s1
c: 6818 ldr r0, [r3, #0]
e: f7ff bffe b.w 0 <result_int_float>
e: R_ARM_THM_JUMP24 result_int_float
12: bf00 nop
armv81mthumb#
00000000 <load_int_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_int_reg0_float_float+0xc>)
2: eeb0 0a60 vmov.f32 s0, s1
6: 6818 ldr r0, [r3, #0]
8: f7ff bffe b.w 0 <result_int_float>
8: R_ARM_THM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg0_float_float>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg0_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 20b58553 fmv.s fa0,fa1
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <load_int_reg0_float_float+0xc>
riscv64#
0000000000000000 <load_int_reg0_float_float>:
0: 20b58553 fmv.s fa0,fa1
4: 00000517 auipc a0,0x0
4: R_RISCV_PCREL_HI20 dummy_int
8: 00052503 lw a0,0(a0) # 4 <load_int_reg0_float_float+0x4>
8: R_RISCV_PCREL_LO12_I .L0
c: 00000317 auipc t1,0x0
c: R_RISCV_CALL_PLT result_int_float
10: 00030067 jr t1 # c <load_int_reg0_float_float+0xc>
tricore#
00000000 <load_int_reg0_float_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <load_int_reg0_float_float>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg0_float_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <load_int_reg0_float_float>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 04 mov %eax,0x4(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg0_float_float+0xa>
a: R_386_PC32 result_int_float
x86_64#
0000000000000000 <load_int_reg0_float_float>:
0: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 6 <load_int_reg0_float_float+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: 0f 28 c1 movaps %xmm1,%xmm0
9: e9 00 00 00 00 jmp e <.LC3+0x2>
a: R_X86_64_PLT32 result_int_float-0x4
load_int_reg1_float_float#
STENCIL void load_int_reg1_float_float(float arg1, float arg2) {
result_float_int(arg1, dummy_int);
}
arm64#
0000000000000000 <load_int_reg1_float_float>:
0: 90000000 adrp x0, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9400000 ldr w0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <load_int_reg1_float_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_int_reg1_float_float+0xc>
4: e5930000 ldr r0, [r3]
8: eafffffe b 0 <result_float_int>
8: R_ARM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <load_int_reg1_float_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5930000 ldr r0, [r3]
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <load_int_reg1_float_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <load_int_reg1_float_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <load_int_reg1_float_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6818 ldr r0, [r3, #0]
a: f7ff bffe b.w 0 <result_float_int>
a: R_ARM_THM_JUMP24 result_float_int
e: bf00 nop
armv81mthumb#
00000000 <load_int_reg1_float_float>:
0: 4b01 ldr r3, [pc, #4] @ (8 <load_int_reg1_float_float+0x8>)
2: 6818 ldr r0, [r3, #0]
4: f7ff bffe b.w 0 <result_float_int>
4: R_ARM_THM_JUMP24 result_float_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <load_int_reg1_float_float>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg1_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_int_reg1_float_float+0x8>
riscv64#
0000000000000000 <load_int_reg1_float_float>:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00052503 lw a0,0(a0) # 0 <load_int_reg1_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <load_int_reg1_float_float+0x8>
tricore#
00000000 <load_int_reg1_float_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <load_int_reg1_float_float>>
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <load_int_reg1_float_float+0x8>
8: R_TRICORE_24REL result_float_int
x86#
00000000 <load_int_reg1_float_float>:
0: a1 00 00 00 00 mov 0x0,%eax
1: R_386_32 dummy_int
5: 89 44 24 08 mov %eax,0x8(%esp)
9: e9 fc ff ff ff jmp a <load_int_reg1_float_float+0xa>
a: R_386_PC32 result_float_int
x86_64#
0000000000000000 <load_int_reg1_float_float>:
0: 8b 3d 00 00 00 00 mov 0x0(%rip),%edi # 6 <load_int_reg1_float_float+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_float_int-0x4
load_float_reg0_float_float#
STENCIL void load_float_reg0_float_float(float arg1, float arg2) {
result_float_float(dummy_float, arg2);
}
arm64#
0000000000000000 <load_float_reg0_float_float>:
0: 90000000 adrp x0, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400000 ldr s0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <load_float_reg0_float_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg0_float_float+0xc>
4: ed930a00 vldr s0, [r3]
8: eafffffe b 0 <result_float_float>
8: R_ARM_JUMP24 result_float_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg0_float_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed930a00 vldr s0, [r3]
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <load_float_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg0_float_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed93 0a00 vldr s0, [r3]
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <load_float_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg0_float_float+0xc>)
2: ed93 0a00 vldr s0, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg0_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg0_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg0_float_float+0x8>
riscv64#
0000000000000000 <load_float_reg0_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a507 flw fa0,0(a5) # 0 <load_float_reg0_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg0_float_float+0x8>
tricore#
00000000 <load_float_reg0_float_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg0_float_float>>
4: R_TRICORE_LO2 dummy_float
8: 54 24 ld.w %d4,[%a2]
a: 1d 00 00 00 j a <load_float_reg0_float_float+0xa>
a: R_TRICORE_24REL result_float_float
x86#
00000000 <load_float_reg0_float_float>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 04 fstps 0x4(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg0_float_float+0xb>
b: R_386_PC32 result_float_float
x86_64#
0000000000000000 <load_float_reg0_float_float>:
0: f3 0f 10 05 00 00 00 movss 0x0(%rip),%xmm0 # 8 <load_float_reg0_float_float+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_float-0x4
load_float_reg1_float_float#
STENCIL void load_float_reg1_float_float(float arg1, float arg2) {
result_float_float(arg1, dummy_float);
}
arm64#
0000000000000000 <load_float_reg1_float_float>:
0: 90000000 adrp x0, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd400001 ldr s1, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <load_float_reg1_float_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <load_float_reg1_float_float+0xc>
4: edd30a00 vldr s1, [r3]
8: eafffffe b 0 <result_float_float>
8: R_ARM_JUMP24 result_float_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <load_float_reg1_float_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: edd30a00 vldr s1, [r3]
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <load_float_reg1_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_float+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <load_float_reg1_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_float+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <load_float_reg1_float_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: edd3 0a00 vldr s1, [r3]
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <load_float_reg1_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <load_float_reg1_float_float+0xc>)
2: edd3 0a00 vldr s1, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <load_float_reg1_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a587 flw fa1,0(a5) # 0 <load_float_reg1_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg1_float_float+0x8>
riscv64#
0000000000000000 <load_float_reg1_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 0007a587 flw fa1,0(a5) # 0 <load_float_reg1_float_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <load_float_reg1_float_float+0x8>
tricore#
00000000 <load_float_reg1_float_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <load_float_reg1_float_float>>
4: R_TRICORE_LO2 dummy_float
8: 54 25 ld.w %d5,[%a2]
a: 1d 00 00 00 j a <load_float_reg1_float_float+0xa>
a: R_TRICORE_24REL result_float_float
x86#
00000000 <load_float_reg1_float_float>:
0: d9 05 00 00 00 00 flds 0x0
2: R_386_32 dummy_float
6: d9 5c 24 08 fstps 0x8(%esp)
a: e9 fc ff ff ff jmp b <load_float_reg1_float_float+0xb>
b: R_386_PC32 result_float_float
x86_64#
0000000000000000 <load_float_reg1_float_float>:
0: f3 0f 10 0d 00 00 00 movss 0x0(%rip),%xmm1 # 8 <load_float_reg1_float_float+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_float-0x4
store_int_reg0_int_int#
STENCIL void store_int_reg0_int_int(int arg1, int arg2) {
dummy_int = arg1;
result_int_int(arg1, arg2);
}
arm64#
0000000000000000 <store_int_reg0_int_int>:
0: 90000003 adrp x3, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9000060 str w0, [x3]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_int>
8: R_AARCH64_JUMP26 result_int_int
armv6#
00000000 <store_int_reg0_int_int>:
0: e59f2004 ldr r2, [pc, #4] @ c <store_int_reg0_int_int+0xc>
4: e5820000 str r0, [r2]
8: eafffffe b 0 <result_int_int>
8: R_ARM_JUMP24 result_int_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <store_int_reg0_int_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5830000 str r0, [r3]
c: eafffffe b 0 <result_int_int>
c: R_ARM_JUMP24 result_int_int
armv7mthumb#
00000000 <store_int_reg0_int_int>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_int+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <store_int_reg0_int_int>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_int+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <store_int_reg0_int_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6018 str r0, [r3, #0]
a: f7ff bffe b.w 0 <result_int_int>
a: R_ARM_THM_JUMP24 result_int_int
e: bf00 nop
armv81mthumb#
00000000 <store_int_reg0_int_int>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_int+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_int>
4: R_ARM_THM_JUMP24 result_int_int
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <store_int_reg0_int_int>:
0: 00000717 auipc a4,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00a72023 sw a0,0(a4) # 0 <store_int_reg0_int_int>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <store_int_reg0_int_int+0x8>
riscv64#
0000000000000000 <store_int_reg0_int_int>:
0: 00000717 auipc a4,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00a72023 sw a0,0(a4) # 0 <store_int_reg0_int_int>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_int
c: 00030067 jr t1 # 8 <store_int_reg0_int_int+0x8>
tricore#
00000000 <store_int_reg0_int_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 59 24 00 00 st.w [%a2]0 <0 <store_int_reg0_int_int>>,%d4
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <store_int_reg0_int_int+0x8>
8: R_TRICORE_24REL result_int_int
x86#
00000000 <store_int_reg0_int_int>:
0: 8b 44 24 04 mov 0x4(%esp),%eax
4: a3 00 00 00 00 mov %eax,0x0
5: R_386_32 dummy_int
9: 89 44 24 04 mov %eax,0x4(%esp)
d: e9 fc ff ff ff jmp e <store_int_reg0_int_int+0xe>
e: R_386_PC32 result_int_int
x86_64#
0000000000000000 <store_int_reg0_int_int>:
0: 89 3d 00 00 00 00 mov %edi,0x0(%rip) # 6 <store_int_reg0_int_int+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_int-0x4
store_int_reg0_int_float#
STENCIL void store_int_reg0_int_float(int arg1, float arg2) {
dummy_int = arg1;
result_int_float(arg1, arg2);
}
arm64#
0000000000000000 <store_int_reg0_int_float>:
0: 90000002 adrp x2, 0 <dummy_int>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_int
4: b9000040 str w0, [x2]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_int
8: 14000000 b 0 <result_int_float>
8: R_AARCH64_JUMP26 result_int_float
armv6#
00000000 <store_int_reg0_int_float>:
0: e59f2004 ldr r2, [pc, #4] @ c <store_int_reg0_int_float+0xc>
4: e5820000 str r0, [r2]
8: eafffffe b 0 <result_int_float>
8: R_ARM_JUMP24 result_int_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_int
armv7#
00000000 <store_int_reg0_int_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_int
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_int
8: e5830000 str r0, [r3]
c: eafffffe b 0 <result_int_float>
c: R_ARM_JUMP24 result_int_float
armv7mthumb#
00000000 <store_int_reg0_int_float>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_float+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7mthumb_fpv5#
00000000 <store_int_reg0_int_float>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_float+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
armv7thumb#
00000000 <store_int_reg0_int_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_int
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_int
8: 6018 str r0, [r3, #0]
a: f7ff bffe b.w 0 <result_int_float>
a: R_ARM_THM_JUMP24 result_int_float
e: bf00 nop
armv81mthumb#
00000000 <store_int_reg0_int_float>:
0: 4a01 ldr r2, [pc, #4] @ (8 <store_int_reg0_int_float+0x8>)
2: 6010 str r0, [r2, #0]
4: f7ff bffe b.w 0 <result_int_float>
4: R_ARM_THM_JUMP24 result_int_float
8: 00000000 .word 0x00000000
8: R_ARM_ABS32 dummy_int
riscv32#
00000000 <store_int_reg0_int_float>:
0: 00000717 auipc a4,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00a72023 sw a0,0(a4) # 0 <store_int_reg0_int_float>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <store_int_reg0_int_float+0x8>
riscv64#
0000000000000000 <store_int_reg0_int_float>:
0: 00000717 auipc a4,0x0
0: R_RISCV_PCREL_HI20 dummy_int
4: 00a72023 sw a0,0(a4) # 0 <store_int_reg0_int_float>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_int_float
c: 00030067 jr t1 # 8 <store_int_reg0_int_float+0x8>
tricore#
00000000 <store_int_reg0_int_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_int
4: 59 24 00 00 st.w [%a2]0 <0 <store_int_reg0_int_float>>,%d4
4: R_TRICORE_LO2 dummy_int
8: 1d 00 00 00 j 8 <store_int_reg0_int_float+0x8>
8: R_TRICORE_24REL result_int_float
x86#
00000000 <store_int_reg0_int_float>:
0: 8b 44 24 04 mov 0x4(%esp),%eax
4: a3 00 00 00 00 mov %eax,0x0
5: R_386_32 dummy_int
9: 89 44 24 04 mov %eax,0x4(%esp)
d: e9 fc ff ff ff jmp e <store_int_reg0_int_float+0xe>
e: R_386_PC32 result_int_float
x86_64#
0000000000000000 <store_int_reg0_int_float>:
0: 89 3d 00 00 00 00 mov %edi,0x0(%rip) # 6 <store_int_reg0_int_float+0x6>
2: R_X86_64_PC32 dummy_int-0x4
6: e9 00 00 00 00 jmp b <.LC2+0x3>
7: R_X86_64_PLT32 result_int_float-0x4
store_float_reg0_float_int#
STENCIL void store_float_reg0_float_int(float arg1, int arg2) {
dummy_float = arg1;
result_float_int(arg1, arg2);
}
arm64#
0000000000000000 <store_float_reg0_float_int>:
0: 90000001 adrp x1, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd000020 str s0, [x1]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_int>
8: R_AARCH64_JUMP26 result_float_int
armv6#
00000000 <store_float_reg0_float_int>:
0: e59f3004 ldr r3, [pc, #4] @ c <store_float_reg0_float_int+0xc>
4: ed830a00 vstr s0, [r3]
8: eafffffe b 0 <result_float_int>
8: R_ARM_JUMP24 result_float_int
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <store_float_reg0_float_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed830a00 vstr s0, [r3]
c: eafffffe b 0 <result_float_int>
c: R_ARM_JUMP24 result_float_int
armv7mthumb#
00000000 <store_float_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <store_float_reg0_float_int+0xc>)
2: ed83 0a00 vstr s0, [r3]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <store_float_reg0_float_int>:
0: 4b02 ldr r3, [pc, #8] @ (c <store_float_reg0_float_int+0xc>)
2: ed83 0a00 vstr s0, [r3]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <store_float_reg0_float_int>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed83 0a00 vstr s0, [r3]
c: f7ff bffe b.w 0 <result_float_int>
c: R_ARM_THM_JUMP24 result_float_int
armv81mthumb#
00000000 <store_float_reg0_float_int>:
0: 4a02 ldr r2, [pc, #8] @ (c <store_float_reg0_float_int+0xc>)
2: ed82 0a00 vstr s0, [r2]
6: f7ff bffe b.w 0 <result_float_int>
6: R_ARM_THM_JUMP24 result_float_int
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <store_float_reg0_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 00078793 mv a5,a5
4: R_RISCV_PCREL_LO12_I .L0
8: e388 fsw fa0,0(a5)
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_int
e: 00030067 jr t1 # a <store_float_reg0_float_int+0xa>
riscv64#
0000000000000000 <store_float_reg0_float_int>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 00a7a027 fsw fa0,0(a5) # 0 <store_float_reg0_float_int>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_int
c: 00030067 jr t1 # 8 <store_float_reg0_float_int+0x8>
tricore#
00000000 <store_float_reg0_float_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <store_float_reg0_float_int>>
4: R_TRICORE_LO2 dummy_float
8: 74 24 st.w [%a2],%d4
a: 1d 00 00 00 j a <store_float_reg0_float_int+0xa>
a: R_TRICORE_24REL result_float_int
x86#
00000000 <store_float_reg0_float_int>:
0: d9 44 24 04 flds 0x4(%esp)
4: d9 15 00 00 00 00 fsts 0x0
6: R_386_32 dummy_float
a: d9 5c 24 04 fstps 0x4(%esp)
e: e9 fc ff ff ff jmp f <store_float_reg0_float_int+0xf>
f: R_386_PC32 result_float_int
x86_64#
0000000000000000 <store_float_reg0_float_int>:
0: f3 0f 11 05 00 00 00 movss %xmm0,0x0(%rip) # 8 <store_float_reg0_float_int+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_int-0x4
store_float_reg0_float_float#
STENCIL void store_float_reg0_float_float(float arg1, float arg2) {
dummy_float = arg1;
result_float_float(arg1, arg2);
}
arm64#
0000000000000000 <store_float_reg0_float_float>:
0: 90000000 adrp x0, 0 <dummy_float>
0: R_AARCH64_ADR_PREL_PG_HI21 dummy_float
4: bd000000 str s0, [x0]
4: R_AARCH64_LDST32_ABS_LO12_NC dummy_float
8: 14000000 b 0 <result_float_float>
8: R_AARCH64_JUMP26 result_float_float
armv6#
00000000 <store_float_reg0_float_float>:
0: e59f3004 ldr r3, [pc, #4] @ c <store_float_reg0_float_float+0xc>
4: ed830a00 vstr s0, [r3]
8: eafffffe b 0 <result_float_float>
8: R_ARM_JUMP24 result_float_float
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7#
00000000 <store_float_reg0_float_float>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC dummy_float
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS dummy_float
8: ed830a00 vstr s0, [r3]
c: eafffffe b 0 <result_float_float>
c: R_ARM_JUMP24 result_float_float
armv7mthumb#
00000000 <store_float_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <store_float_reg0_float_float+0xc>)
2: ed83 0a00 vstr s0, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7mthumb_fpv5#
00000000 <store_float_reg0_float_float>:
0: 4b02 ldr r3, [pc, #8] @ (c <store_float_reg0_float_float+0xc>)
2: ed83 0a00 vstr s0, [r3]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
armv7thumb#
00000000 <store_float_reg0_float_float>:
0: f240 0300 movw r3, #0
0: R_ARM_THM_MOVW_ABS_NC dummy_float
4: f2c0 0300 movt r3, #0
4: R_ARM_THM_MOVT_ABS dummy_float
8: ed83 0a00 vstr s0, [r3]
c: f7ff bffe b.w 0 <result_float_float>
c: R_ARM_THM_JUMP24 result_float_float
armv81mthumb#
00000000 <store_float_reg0_float_float>:
0: 4a02 ldr r2, [pc, #8] @ (c <store_float_reg0_float_float+0xc>)
2: ed82 0a00 vstr s0, [r2]
6: f7ff bffe b.w 0 <result_float_float>
6: R_ARM_THM_JUMP24 result_float_float
a: bf00 nop
c: 00000000 .word 0x00000000
c: R_ARM_ABS32 dummy_float
riscv32#
00000000 <store_float_reg0_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 00078793 mv a5,a5
4: R_RISCV_PCREL_LO12_I .L0
8: e388 fsw fa0,0(a5)
a: 00000317 auipc t1,0x0
a: R_RISCV_CALL_PLT result_float_float
e: 00030067 jr t1 # a <store_float_reg0_float_float+0xa>
riscv64#
0000000000000000 <store_float_reg0_float_float>:
0: 00000797 auipc a5,0x0
0: R_RISCV_PCREL_HI20 dummy_float
4: 00a7a027 fsw fa0,0(a5) # 0 <store_float_reg0_float_float>
4: R_RISCV_PCREL_LO12_S .L0
8: 00000317 auipc t1,0x0
8: R_RISCV_CALL_PLT result_float_float
c: 00030067 jr t1 # 8 <store_float_reg0_float_float+0x8>
tricore#
00000000 <store_float_reg0_float_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ dummy_float
4: d9 22 00 00 lea %a2,[%a2]0 <0 <store_float_reg0_float_float>>
4: R_TRICORE_LO2 dummy_float
8: 74 24 st.w [%a2],%d4
a: 1d 00 00 00 j a <store_float_reg0_float_float+0xa>
a: R_TRICORE_24REL result_float_float
x86#
00000000 <store_float_reg0_float_float>:
0: d9 44 24 04 flds 0x4(%esp)
4: d9 15 00 00 00 00 fsts 0x0
6: R_386_32 dummy_float
a: d9 5c 24 04 fstps 0x4(%esp)
e: e9 fc ff ff ff jmp f <store_float_reg0_float_float+0xf>
f: R_386_PC32 result_float_float
x86_64#
0000000000000000 <store_float_reg0_float_float>:
0: f3 0f 11 05 00 00 00 movss %xmm0,0x0(%rip) # 8 <store_float_reg0_float_float+0x8>
7: 00
4: R_X86_64_PC32 dummy_float-0x4
8: e9 00 00 00 00 jmp d <.LC3+0x1>
9: R_X86_64_PLT32 result_float_float-0x4