Array element-wise stencils#
add_intarr_intarr#
STENCIL void add_intarr_intarr(void) {
// Element-wise add of int array and int array
aux_arr_add_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <add_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_add_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <add_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <add_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <add_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <add_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <add_intarr_intarr+0x30>
18: ebfffffe bl 0 <add_intarr_intarr>
18: R_ARM_CALL aux_arr_add_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <add_intarr_intarr>
28: R_ARM_CALL aux_arr_add_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <add_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <add_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_add_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <add_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_vv
28: 000080e7 jalr ra # 24 <add_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_intarr_intarr+0x30>
riscv64#
0000000000000000 <add_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_vv
28: 000080e7 jalr ra # 24 <add_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_intarr_intarr+0x30>
tricore#
00000000 <add_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <add_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_add_int_int_vv
24: 1d 00 00 00 j 24 <add_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <add_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <add_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_add_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <add_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <add_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <add_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <add_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <add_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <add_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_add_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
add_intarr_int#
STENCIL void add_intarr_int(void) {
// Element-wise add of int array and int scalar
aux_arr_add_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <add_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_intarr_int>
28: R_AARCH64_CALL26 aux_arr_add_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <add_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <add_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <add_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <add_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_intarr_int+0x34>
1c: ebfffffe bl 0 <add_intarr_int>
1c: R_ARM_CALL aux_arr_add_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <add_intarr_int>
2c: R_ARM_CALL aux_arr_add_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <add_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <add_intarr_int+0x28>)
e: f7ff fffe bl 0 <add_intarr_int>
e: R_ARM_THM_CALL aux_arr_add_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <add_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <add_intarr_int>
e: R_ARM_THM_CALL aux_arr_add_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <add_intarr_int>
26: R_ARM_THM_CALL aux_arr_add_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <add_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <add_intarr_int+0x28>)
e: f7ff fffe bl 0 <add_intarr_int>
e: R_ARM_THM_CALL aux_arr_add_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <add_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_vs
28: 000080e7 jalr ra # 24 <add_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_intarr_int+0x30>
riscv64#
0000000000000000 <add_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <add_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_vs
28: 000080e7 jalr ra # 24 <add_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_intarr_int+0x30>
tricore#
00000000 <add_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_add_int_int_vs
24: 1d 00 00 00 j 24 <add_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <add_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_add_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <add_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <add_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <add_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <add_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <add_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_add_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
add_int_intarr#
STENCIL void add_int_intarr(void) {
// Element-wise add of int scalar and int array
aux_arr_add_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <add_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <add_int_intarr>
28: R_AARCH64_CALL26 aux_arr_add_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <add_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <add_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <add_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <add_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <add_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <add_int_intarr>
1c: R_ARM_CALL aux_arr_add_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <add_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <add_int_intarr>
2c: R_ARM_CALL aux_arr_add_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <add_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_intarr>
e: R_ARM_THM_CALL aux_arr_add_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <add_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_intarr>
e: R_ARM_THM_CALL aux_arr_add_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <add_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <add_int_intarr>
26: R_ARM_THM_CALL aux_arr_add_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <add_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_intarr>
e: R_ARM_THM_CALL aux_arr_add_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <add_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <add_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_sv
28: 000080e7 jalr ra # 24 <add_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_int_intarr+0x30>
riscv64#
0000000000000000 <add_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <add_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_int_sv
28: 000080e7 jalr ra # 24 <add_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <add_int_intarr+0x30>
tricore#
00000000 <add_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <add_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_add_int_int_sv
24: 1d 00 00 00 j 24 <add_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <add_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_add_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <add_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <add_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <add_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <add_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <add_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_add_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
add_intarr_floatarr#
STENCIL void add_intarr_floatarr(void) {
// Element-wise add of int array and float array
aux_arr_add_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_add_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <add_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <add_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <add_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <add_intarr_floatarr+0x30>
18: ebfffffe bl 0 <add_intarr_floatarr>
18: R_ARM_CALL aux_arr_add_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <add_intarr_floatarr>
28: R_ARM_CALL aux_arr_add_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <add_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_add_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_vv
28: 000080e7 jalr ra # 24 <add_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_intarr_floatarr+0x30>
riscv64#
0000000000000000 <add_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_vv
28: 000080e7 jalr ra # 24 <add_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_intarr_floatarr+0x30>
tricore#
00000000 <add_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <add_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_add_int_float_vv
24: 1d 00 00 00 j 24 <add_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <add_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_add_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <add_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <add_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <add_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <add_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <add_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_add_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
add_intarr_float#
STENCIL void add_intarr_float(void) {
// Element-wise add of int array and float scalar
aux_arr_add_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_intarr_float>
28: R_AARCH64_CALL26 aux_arr_add_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <add_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <add_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <add_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_intarr_float+0x34>
1c: ebfffffe bl 0 <add_intarr_float>
1c: R_ARM_CALL aux_arr_add_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <add_intarr_float>
2c: R_ARM_CALL aux_arr_add_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_intarr_float+0x28>)
10: f7ff fffe bl 0 <add_intarr_float>
10: R_ARM_THM_CALL aux_arr_add_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <add_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <add_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <add_intarr_float>
10: R_ARM_THM_CALL aux_arr_add_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <add_intarr_float>
28: R_ARM_THM_CALL aux_arr_add_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_intarr_float+0x28>)
10: f7ff fffe bl 0 <add_intarr_float>
10: R_ARM_THM_CALL aux_arr_add_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <add_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <add_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_vs
28: 000080e7 jalr ra # 24 <add_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_intarr_float+0x30>
riscv64#
0000000000000000 <add_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <add_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <add_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_vs
28: 000080e7 jalr ra # 24 <add_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_intarr_float+0x30>
tricore#
00000000 <add_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <add_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <add_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <add_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <add_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_add_int_float_vs
26: 1d 00 00 00 j 26 <add_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_add_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <add_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <add_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <add_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <add_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_add_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
add_int_floatarr#
STENCIL void add_int_floatarr(void) {
// Element-wise add of int scalar and float array
aux_arr_add_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <add_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_add_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <add_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <add_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <add_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <add_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <add_int_floatarr>
1c: R_ARM_CALL aux_arr_add_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <add_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <add_int_floatarr>
2c: R_ARM_CALL aux_arr_add_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_floatarr>
e: R_ARM_THM_CALL aux_arr_add_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <add_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_floatarr>
e: R_ARM_THM_CALL aux_arr_add_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <add_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <add_int_floatarr>
26: R_ARM_THM_CALL aux_arr_add_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <add_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <add_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <add_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <add_int_floatarr>
e: R_ARM_THM_CALL aux_arr_add_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <add_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <add_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_sv
28: 000080e7 jalr ra # 24 <add_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_int_floatarr+0x30>
riscv64#
0000000000000000 <add_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <add_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_int_float_sv
28: 000080e7 jalr ra # 24 <add_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_int_floatarr+0x30>
tricore#
00000000 <add_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <add_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_add_int_float_sv
24: 1d 00 00 00 j 24 <add_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_add_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <add_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <add_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <add_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <add_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_add_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
add_floatarr_intarr#
STENCIL void add_floatarr_intarr(void) {
// Element-wise add of float array and int array
aux_arr_add_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_add_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <add_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <add_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <add_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <add_floatarr_intarr+0x30>
18: ebfffffe bl 0 <add_floatarr_intarr>
18: R_ARM_CALL aux_arr_add_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <add_floatarr_intarr>
28: R_ARM_CALL aux_arr_add_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <add_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_add_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_add_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_vv
28: 000080e7 jalr ra # 24 <add_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_intarr+0x30>
riscv64#
0000000000000000 <add_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_vv
28: 000080e7 jalr ra # 24 <add_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_intarr+0x30>
tricore#
00000000 <add_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <add_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_add_float_int_vv
24: 1d 00 00 00 j 24 <add_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <add_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_add_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <add_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <add_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <add_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <add_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <add_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_add_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
add_floatarr_int#
STENCIL void add_floatarr_int(void) {
// Element-wise add of float array and int scalar
aux_arr_add_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_add_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <add_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <add_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <add_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_floatarr_int+0x34>
1c: ebfffffe bl 0 <add_floatarr_int>
1c: R_ARM_CALL aux_arr_add_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <add_floatarr_int>
2c: R_ARM_CALL aux_arr_add_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <add_floatarr_int+0x28>)
e: f7ff fffe bl 0 <add_floatarr_int>
e: R_ARM_THM_CALL aux_arr_add_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <add_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <add_floatarr_int>
e: R_ARM_THM_CALL aux_arr_add_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <add_floatarr_int>
26: R_ARM_THM_CALL aux_arr_add_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <add_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <add_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <add_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <add_floatarr_int+0x28>)
e: f7ff fffe bl 0 <add_floatarr_int>
e: R_ARM_THM_CALL aux_arr_add_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <add_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_vs
28: 000080e7 jalr ra # 24 <add_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_int+0x30>
riscv64#
0000000000000000 <add_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <add_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_vs
28: 000080e7 jalr ra # 24 <add_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_int+0x30>
tricore#
00000000 <add_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_add_float_int_vs
24: 1d 00 00 00 j 24 <add_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_add_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <add_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <add_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <add_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <add_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_add_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
add_float_intarr#
STENCIL void add_float_intarr(void) {
// Element-wise add of float scalar and int array
aux_arr_add_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <add_float_intarr>
28: R_AARCH64_CALL26 aux_arr_add_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <add_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <add_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <add_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_float_intarr+0x34>
1c: ebfffffe bl 0 <add_float_intarr>
1c: R_ARM_CALL aux_arr_add_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <add_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <add_float_intarr>
2c: R_ARM_CALL aux_arr_add_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_float_intarr+0x28>)
10: f7ff fffe bl 0 <add_float_intarr>
10: R_ARM_THM_CALL aux_arr_add_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <add_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <add_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <add_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <add_float_intarr>
10: R_ARM_THM_CALL aux_arr_add_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <add_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <add_float_intarr>
28: R_ARM_THM_CALL aux_arr_add_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_float_intarr+0x28>)
10: f7ff fffe bl 0 <add_float_intarr>
10: R_ARM_THM_CALL aux_arr_add_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <add_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <add_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <add_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_sv
28: 000080e7 jalr ra # 24 <add_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_float_intarr+0x30>
riscv64#
0000000000000000 <add_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <add_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <add_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_int_sv
28: 000080e7 jalr ra # 24 <add_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_float_intarr+0x30>
tricore#
00000000 <add_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <add_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <add_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <add_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <add_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_add_float_int_sv
26: 1d 00 00 00 j 26 <add_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_add_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <add_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <add_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <add_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <add_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_add_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
add_floatarr_floatarr#
STENCIL void add_floatarr_floatarr(void) {
// Element-wise add of float array and float array
aux_arr_add_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_add_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <add_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <add_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <add_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <add_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <add_floatarr_floatarr>
18: R_ARM_CALL aux_arr_add_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <add_floatarr_floatarr>
28: R_ARM_CALL aux_arr_add_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <add_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_add_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <add_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <add_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <add_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <add_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <add_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_add_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <add_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_vv
28: 000080e7 jalr ra # 24 <add_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <add_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <add_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_vv
28: 000080e7 jalr ra # 24 <add_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_floatarr+0x30>
tricore#
00000000 <add_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <add_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <add_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <add_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <add_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <add_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_add_float_float_vv
24: 1d 00 00 00 j 24 <add_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <add_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_add_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <add_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <add_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <add_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <add_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <add_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_add_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
add_floatarr_float#
STENCIL void add_floatarr_float(void) {
// Element-wise add of float array and float scalar
aux_arr_add_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <add_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_add_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <add_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <add_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <add_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_floatarr_float+0x34>
1c: ebfffffe bl 0 <add_floatarr_float>
1c: R_ARM_CALL aux_arr_add_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <add_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <add_floatarr_float>
2c: R_ARM_CALL aux_arr_add_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_floatarr_float+0x28>)
10: f7ff fffe bl 0 <add_floatarr_float>
10: R_ARM_THM_CALL aux_arr_add_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <add_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <add_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <add_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <add_floatarr_float>
10: R_ARM_THM_CALL aux_arr_add_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <add_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <add_floatarr_float>
28: R_ARM_THM_CALL aux_arr_add_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_floatarr_float+0x28>)
10: f7ff fffe bl 0 <add_floatarr_float>
10: R_ARM_THM_CALL aux_arr_add_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <add_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <add_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <add_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_vs
28: 000080e7 jalr ra # 24 <add_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_float+0x30>
riscv64#
0000000000000000 <add_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <add_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <add_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_vs
28: 000080e7 jalr ra # 24 <add_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_floatarr_float+0x30>
tricore#
00000000 <add_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <add_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <add_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <add_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <add_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_add_float_float_vs
26: 1d 00 00 00 j 26 <add_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_add_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <add_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <add_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <add_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <add_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_add_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
add_float_floatarr#
STENCIL void add_float_floatarr(void) {
// Element-wise add of float scalar and float array
aux_arr_add_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <add_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <add_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_add_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <add_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <add_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <add_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <add_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <add_float_floatarr+0x34>
1c: ebfffffe bl 0 <add_float_floatarr>
1c: R_ARM_CALL aux_arr_add_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <add_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <add_float_floatarr>
2c: R_ARM_CALL aux_arr_add_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <add_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_float_floatarr+0x28>)
10: f7ff fffe bl 0 <add_float_floatarr>
10: R_ARM_THM_CALL aux_arr_add_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <add_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <add_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <add_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <add_float_floatarr>
10: R_ARM_THM_CALL aux_arr_add_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <add_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <add_float_floatarr>
28: R_ARM_THM_CALL aux_arr_add_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <add_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <add_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <add_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <add_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <add_float_floatarr+0x28>)
10: f7ff fffe bl 0 <add_float_floatarr>
10: R_ARM_THM_CALL aux_arr_add_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <add_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <add_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <add_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_sv
28: 000080e7 jalr ra # 24 <add_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_float_floatarr+0x30>
riscv64#
0000000000000000 <add_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <add_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <add_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_add_float_float_sv
28: 000080e7 jalr ra # 24 <add_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <add_float_floatarr+0x30>
tricore#
00000000 <add_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <add_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <add_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <add_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <add_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <add_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_add_float_float_sv
26: 1d 00 00 00 j 26 <add_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <add_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <add_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_add_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <add_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <add_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <add_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <add_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <add_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <add_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <add_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_add_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
sub_intarr_intarr#
STENCIL void sub_intarr_intarr(void) {
// Element-wise sub of int array and int array
aux_arr_sub_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <sub_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_sub_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <sub_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <sub_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <sub_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <sub_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <sub_intarr_intarr+0x30>
18: ebfffffe bl 0 <sub_intarr_intarr>
18: R_ARM_CALL aux_arr_sub_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <sub_intarr_intarr>
28: R_ARM_CALL aux_arr_sub_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <sub_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <sub_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_sub_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <sub_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_vv
28: 000080e7 jalr ra # 24 <sub_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_intarr_intarr+0x30>
riscv64#
0000000000000000 <sub_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_vv
28: 000080e7 jalr ra # 24 <sub_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_intarr_intarr+0x30>
tricore#
00000000 <sub_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <sub_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_int_int_vv
24: 1d 00 00 00 j 24 <sub_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <sub_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <sub_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_sub_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <sub_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <sub_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <sub_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <sub_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <sub_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <sub_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_sub_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
sub_intarr_int#
STENCIL void sub_intarr_int(void) {
// Element-wise sub of int array and int scalar
aux_arr_sub_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <sub_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_intarr_int>
28: R_AARCH64_CALL26 aux_arr_sub_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <sub_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <sub_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <sub_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <sub_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_intarr_int+0x34>
1c: ebfffffe bl 0 <sub_intarr_int>
1c: R_ARM_CALL aux_arr_sub_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <sub_intarr_int>
2c: R_ARM_CALL aux_arr_sub_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <sub_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_intarr_int+0x28>)
e: f7ff fffe bl 0 <sub_intarr_int>
e: R_ARM_THM_CALL aux_arr_sub_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <sub_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <sub_intarr_int>
e: R_ARM_THM_CALL aux_arr_sub_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <sub_intarr_int>
26: R_ARM_THM_CALL aux_arr_sub_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <sub_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_intarr_int+0x28>)
e: f7ff fffe bl 0 <sub_intarr_int>
e: R_ARM_THM_CALL aux_arr_sub_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <sub_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_vs
28: 000080e7 jalr ra # 24 <sub_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_intarr_int+0x30>
riscv64#
0000000000000000 <sub_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <sub_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_vs
28: 000080e7 jalr ra # 24 <sub_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_intarr_int+0x30>
tricore#
00000000 <sub_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_sub_int_int_vs
24: 1d 00 00 00 j 24 <sub_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <sub_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_sub_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <sub_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <sub_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <sub_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <sub_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <sub_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_sub_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
sub_int_intarr#
STENCIL void sub_int_intarr(void) {
// Element-wise sub of int scalar and int array
aux_arr_sub_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <sub_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <sub_int_intarr>
28: R_AARCH64_CALL26 aux_arr_sub_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <sub_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <sub_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <sub_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <sub_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <sub_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <sub_int_intarr>
1c: R_ARM_CALL aux_arr_sub_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <sub_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <sub_int_intarr>
2c: R_ARM_CALL aux_arr_sub_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <sub_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_intarr>
e: R_ARM_THM_CALL aux_arr_sub_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <sub_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_intarr>
e: R_ARM_THM_CALL aux_arr_sub_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <sub_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <sub_int_intarr>
26: R_ARM_THM_CALL aux_arr_sub_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <sub_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_intarr>
e: R_ARM_THM_CALL aux_arr_sub_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <sub_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <sub_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_sv
28: 000080e7 jalr ra # 24 <sub_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_int_intarr+0x30>
riscv64#
0000000000000000 <sub_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <sub_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_int_sv
28: 000080e7 jalr ra # 24 <sub_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <sub_int_intarr+0x30>
tricore#
00000000 <sub_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <sub_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_int_int_sv
24: 1d 00 00 00 j 24 <sub_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <sub_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_sub_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <sub_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <sub_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <sub_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <sub_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <sub_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_sub_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
sub_intarr_floatarr#
STENCIL void sub_intarr_floatarr(void) {
// Element-wise sub of int array and float array
aux_arr_sub_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_sub_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <sub_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <sub_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <sub_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <sub_intarr_floatarr+0x30>
18: ebfffffe bl 0 <sub_intarr_floatarr>
18: R_ARM_CALL aux_arr_sub_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <sub_intarr_floatarr>
28: R_ARM_CALL aux_arr_sub_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <sub_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_sub_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_vv
28: 000080e7 jalr ra # 24 <sub_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_intarr_floatarr+0x30>
riscv64#
0000000000000000 <sub_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_vv
28: 000080e7 jalr ra # 24 <sub_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_intarr_floatarr+0x30>
tricore#
00000000 <sub_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <sub_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_int_float_vv
24: 1d 00 00 00 j 24 <sub_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <sub_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_sub_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <sub_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <sub_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <sub_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <sub_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <sub_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_sub_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
sub_intarr_float#
STENCIL void sub_intarr_float(void) {
// Element-wise sub of int array and float scalar
aux_arr_sub_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_intarr_float>
28: R_AARCH64_CALL26 aux_arr_sub_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <sub_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <sub_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <sub_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_intarr_float+0x34>
1c: ebfffffe bl 0 <sub_intarr_float>
1c: R_ARM_CALL aux_arr_sub_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <sub_intarr_float>
2c: R_ARM_CALL aux_arr_sub_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_intarr_float+0x28>)
10: f7ff fffe bl 0 <sub_intarr_float>
10: R_ARM_THM_CALL aux_arr_sub_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <sub_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <sub_intarr_float>
10: R_ARM_THM_CALL aux_arr_sub_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <sub_intarr_float>
28: R_ARM_THM_CALL aux_arr_sub_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_intarr_float+0x28>)
10: f7ff fffe bl 0 <sub_intarr_float>
10: R_ARM_THM_CALL aux_arr_sub_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <sub_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <sub_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_vs
28: 000080e7 jalr ra # 24 <sub_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_intarr_float+0x30>
riscv64#
0000000000000000 <sub_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <sub_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <sub_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_vs
28: 000080e7 jalr ra # 24 <sub_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_intarr_float+0x30>
tricore#
00000000 <sub_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <sub_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <sub_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_sub_int_float_vs
26: 1d 00 00 00 j 26 <sub_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_sub_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <sub_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <sub_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <sub_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <sub_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_sub_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
sub_int_floatarr#
STENCIL void sub_int_floatarr(void) {
// Element-wise sub of int scalar and float array
aux_arr_sub_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <sub_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_sub_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <sub_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <sub_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <sub_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <sub_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <sub_int_floatarr>
1c: R_ARM_CALL aux_arr_sub_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <sub_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <sub_int_floatarr>
2c: R_ARM_CALL aux_arr_sub_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_floatarr>
e: R_ARM_THM_CALL aux_arr_sub_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <sub_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_floatarr>
e: R_ARM_THM_CALL aux_arr_sub_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <sub_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <sub_int_floatarr>
26: R_ARM_THM_CALL aux_arr_sub_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <sub_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <sub_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <sub_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <sub_int_floatarr>
e: R_ARM_THM_CALL aux_arr_sub_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <sub_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <sub_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_sv
28: 000080e7 jalr ra # 24 <sub_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_int_floatarr+0x30>
riscv64#
0000000000000000 <sub_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <sub_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_int_float_sv
28: 000080e7 jalr ra # 24 <sub_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_int_floatarr+0x30>
tricore#
00000000 <sub_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <sub_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_int_float_sv
24: 1d 00 00 00 j 24 <sub_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_sub_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <sub_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <sub_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <sub_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <sub_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_sub_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
sub_floatarr_intarr#
STENCIL void sub_floatarr_intarr(void) {
// Element-wise sub of float array and int array
aux_arr_sub_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_sub_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <sub_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <sub_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <sub_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <sub_floatarr_intarr+0x30>
18: ebfffffe bl 0 <sub_floatarr_intarr>
18: R_ARM_CALL aux_arr_sub_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <sub_floatarr_intarr>
28: R_ARM_CALL aux_arr_sub_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <sub_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_sub_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_sub_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_vv
28: 000080e7 jalr ra # 24 <sub_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_intarr+0x30>
riscv64#
0000000000000000 <sub_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_vv
28: 000080e7 jalr ra # 24 <sub_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_intarr+0x30>
tricore#
00000000 <sub_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <sub_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_float_int_vv
24: 1d 00 00 00 j 24 <sub_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <sub_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_sub_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <sub_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <sub_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <sub_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <sub_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <sub_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_sub_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
sub_floatarr_int#
STENCIL void sub_floatarr_int(void) {
// Element-wise sub of float array and int scalar
aux_arr_sub_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_sub_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <sub_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <sub_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <sub_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_floatarr_int+0x34>
1c: ebfffffe bl 0 <sub_floatarr_int>
1c: R_ARM_CALL aux_arr_sub_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <sub_floatarr_int>
2c: R_ARM_CALL aux_arr_sub_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_floatarr_int+0x28>)
e: f7ff fffe bl 0 <sub_floatarr_int>
e: R_ARM_THM_CALL aux_arr_sub_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <sub_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <sub_floatarr_int>
e: R_ARM_THM_CALL aux_arr_sub_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <sub_floatarr_int>
26: R_ARM_THM_CALL aux_arr_sub_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <sub_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <sub_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <sub_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_floatarr_int+0x28>)
e: f7ff fffe bl 0 <sub_floatarr_int>
e: R_ARM_THM_CALL aux_arr_sub_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <sub_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_vs
28: 000080e7 jalr ra # 24 <sub_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_int+0x30>
riscv64#
0000000000000000 <sub_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <sub_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_vs
28: 000080e7 jalr ra # 24 <sub_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_int+0x30>
tricore#
00000000 <sub_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_sub_float_int_vs
24: 1d 00 00 00 j 24 <sub_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_sub_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <sub_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <sub_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <sub_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <sub_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_sub_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
sub_float_intarr#
STENCIL void sub_float_intarr(void) {
// Element-wise sub of float scalar and int array
aux_arr_sub_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <sub_float_intarr>
28: R_AARCH64_CALL26 aux_arr_sub_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <sub_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <sub_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <sub_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_float_intarr+0x34>
1c: ebfffffe bl 0 <sub_float_intarr>
1c: R_ARM_CALL aux_arr_sub_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <sub_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <sub_float_intarr>
2c: R_ARM_CALL aux_arr_sub_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_float_intarr+0x28>)
10: f7ff fffe bl 0 <sub_float_intarr>
10: R_ARM_THM_CALL aux_arr_sub_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <sub_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <sub_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <sub_float_intarr>
10: R_ARM_THM_CALL aux_arr_sub_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <sub_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <sub_float_intarr>
28: R_ARM_THM_CALL aux_arr_sub_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_float_intarr+0x28>)
10: f7ff fffe bl 0 <sub_float_intarr>
10: R_ARM_THM_CALL aux_arr_sub_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <sub_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <sub_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <sub_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_sv
28: 000080e7 jalr ra # 24 <sub_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_float_intarr+0x30>
riscv64#
0000000000000000 <sub_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <sub_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <sub_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_int_sv
28: 000080e7 jalr ra # 24 <sub_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_float_intarr+0x30>
tricore#
00000000 <sub_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <sub_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <sub_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_sub_float_int_sv
26: 1d 00 00 00 j 26 <sub_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_sub_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <sub_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <sub_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <sub_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <sub_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_sub_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
sub_floatarr_floatarr#
STENCIL void sub_floatarr_floatarr(void) {
// Element-wise sub of float array and float array
aux_arr_sub_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_sub_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <sub_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <sub_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <sub_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <sub_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <sub_floatarr_floatarr>
18: R_ARM_CALL aux_arr_sub_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <sub_floatarr_floatarr>
28: R_ARM_CALL aux_arr_sub_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <sub_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_sub_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sub_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <sub_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <sub_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <sub_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <sub_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_sub_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <sub_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_vv
28: 000080e7 jalr ra # 24 <sub_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <sub_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <sub_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_vv
28: 000080e7 jalr ra # 24 <sub_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_floatarr+0x30>
tricore#
00000000 <sub_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sub_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <sub_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <sub_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_sub_float_float_vv
24: 1d 00 00 00 j 24 <sub_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <sub_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_sub_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <sub_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <sub_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <sub_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <sub_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <sub_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_sub_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
sub_floatarr_float#
STENCIL void sub_floatarr_float(void) {
// Element-wise sub of float array and float scalar
aux_arr_sub_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <sub_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_sub_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <sub_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <sub_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <sub_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_floatarr_float+0x34>
1c: ebfffffe bl 0 <sub_floatarr_float>
1c: R_ARM_CALL aux_arr_sub_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sub_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <sub_floatarr_float>
2c: R_ARM_CALL aux_arr_sub_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_floatarr_float+0x28>)
10: f7ff fffe bl 0 <sub_floatarr_float>
10: R_ARM_THM_CALL aux_arr_sub_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sub_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <sub_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <sub_floatarr_float>
10: R_ARM_THM_CALL aux_arr_sub_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sub_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <sub_floatarr_float>
28: R_ARM_THM_CALL aux_arr_sub_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_floatarr_float+0x28>)
10: f7ff fffe bl 0 <sub_floatarr_float>
10: R_ARM_THM_CALL aux_arr_sub_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sub_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <sub_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <sub_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_vs
28: 000080e7 jalr ra # 24 <sub_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_float+0x30>
riscv64#
0000000000000000 <sub_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <sub_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <sub_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_vs
28: 000080e7 jalr ra # 24 <sub_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_floatarr_float+0x30>
tricore#
00000000 <sub_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <sub_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <sub_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_sub_float_float_vs
26: 1d 00 00 00 j 26 <sub_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_sub_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <sub_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <sub_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <sub_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <sub_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_sub_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
sub_float_floatarr#
STENCIL void sub_float_floatarr(void) {
// Element-wise sub of float scalar and float array
aux_arr_sub_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <sub_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <sub_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_sub_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sub_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <sub_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <sub_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <sub_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <sub_float_floatarr+0x34>
1c: ebfffffe bl 0 <sub_float_floatarr>
1c: R_ARM_CALL aux_arr_sub_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <sub_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <sub_float_floatarr>
2c: R_ARM_CALL aux_arr_sub_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sub_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_float_floatarr+0x28>)
10: f7ff fffe bl 0 <sub_float_floatarr>
10: R_ARM_THM_CALL aux_arr_sub_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <sub_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <sub_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <sub_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <sub_float_floatarr>
10: R_ARM_THM_CALL aux_arr_sub_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <sub_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <sub_float_floatarr>
28: R_ARM_THM_CALL aux_arr_sub_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sub_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <sub_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <sub_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <sub_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <sub_float_floatarr+0x28>)
10: f7ff fffe bl 0 <sub_float_floatarr>
10: R_ARM_THM_CALL aux_arr_sub_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <sub_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <sub_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <sub_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_sv
28: 000080e7 jalr ra # 24 <sub_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_float_floatarr+0x30>
riscv64#
0000000000000000 <sub_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <sub_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <sub_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_sub_float_float_sv
28: 000080e7 jalr ra # 24 <sub_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <sub_float_floatarr+0x30>
tricore#
00000000 <sub_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <sub_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <sub_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <sub_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <sub_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <sub_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_sub_float_float_sv
26: 1d 00 00 00 j 26 <sub_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <sub_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <sub_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_sub_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <sub_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sub_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sub_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <sub_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <sub_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <sub_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <sub_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_sub_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
mul_intarr_intarr#
STENCIL void mul_intarr_intarr(void) {
// Element-wise mul of int array and int array
aux_arr_mul_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <mul_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_mul_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <mul_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <mul_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <mul_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <mul_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <mul_intarr_intarr+0x30>
18: ebfffffe bl 0 <mul_intarr_intarr>
18: R_ARM_CALL aux_arr_mul_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <mul_intarr_intarr>
28: R_ARM_CALL aux_arr_mul_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <mul_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <mul_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_mul_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <mul_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_vv
28: 000080e7 jalr ra # 24 <mul_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_intarr_intarr+0x30>
riscv64#
0000000000000000 <mul_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_vv
28: 000080e7 jalr ra # 24 <mul_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_intarr_intarr+0x30>
tricore#
00000000 <mul_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <mul_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_int_int_vv
24: 1d 00 00 00 j 24 <mul_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <mul_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <mul_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_mul_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <mul_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <mul_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <mul_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <mul_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <mul_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <mul_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_mul_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
mul_intarr_int#
STENCIL void mul_intarr_int(void) {
// Element-wise mul of int array and int scalar
aux_arr_mul_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <mul_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_intarr_int>
28: R_AARCH64_CALL26 aux_arr_mul_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <mul_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <mul_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <mul_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <mul_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_intarr_int+0x34>
1c: ebfffffe bl 0 <mul_intarr_int>
1c: R_ARM_CALL aux_arr_mul_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <mul_intarr_int>
2c: R_ARM_CALL aux_arr_mul_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <mul_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_intarr_int+0x28>)
e: f7ff fffe bl 0 <mul_intarr_int>
e: R_ARM_THM_CALL aux_arr_mul_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <mul_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <mul_intarr_int>
e: R_ARM_THM_CALL aux_arr_mul_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <mul_intarr_int>
26: R_ARM_THM_CALL aux_arr_mul_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <mul_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_intarr_int+0x28>)
e: f7ff fffe bl 0 <mul_intarr_int>
e: R_ARM_THM_CALL aux_arr_mul_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <mul_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_vs
28: 000080e7 jalr ra # 24 <mul_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_intarr_int+0x30>
riscv64#
0000000000000000 <mul_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <mul_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_vs
28: 000080e7 jalr ra # 24 <mul_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_intarr_int+0x30>
tricore#
00000000 <mul_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_mul_int_int_vs
24: 1d 00 00 00 j 24 <mul_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <mul_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_mul_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <mul_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <mul_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <mul_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <mul_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <mul_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_mul_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
mul_int_intarr#
STENCIL void mul_int_intarr(void) {
// Element-wise mul of int scalar and int array
aux_arr_mul_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <mul_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <mul_int_intarr>
28: R_AARCH64_CALL26 aux_arr_mul_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <mul_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <mul_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <mul_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <mul_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <mul_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <mul_int_intarr>
1c: R_ARM_CALL aux_arr_mul_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <mul_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <mul_int_intarr>
2c: R_ARM_CALL aux_arr_mul_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <mul_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_intarr>
e: R_ARM_THM_CALL aux_arr_mul_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <mul_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_intarr>
e: R_ARM_THM_CALL aux_arr_mul_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <mul_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <mul_int_intarr>
26: R_ARM_THM_CALL aux_arr_mul_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <mul_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_intarr>
e: R_ARM_THM_CALL aux_arr_mul_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <mul_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <mul_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_sv
28: 000080e7 jalr ra # 24 <mul_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_int_intarr+0x30>
riscv64#
0000000000000000 <mul_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <mul_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_int_sv
28: 000080e7 jalr ra # 24 <mul_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <mul_int_intarr+0x30>
tricore#
00000000 <mul_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <mul_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_int_int_sv
24: 1d 00 00 00 j 24 <mul_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <mul_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_mul_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <mul_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <mul_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <mul_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <mul_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <mul_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_mul_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
mul_intarr_floatarr#
STENCIL void mul_intarr_floatarr(void) {
// Element-wise mul of int array and float array
aux_arr_mul_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_mul_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <mul_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <mul_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <mul_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <mul_intarr_floatarr+0x30>
18: ebfffffe bl 0 <mul_intarr_floatarr>
18: R_ARM_CALL aux_arr_mul_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <mul_intarr_floatarr>
28: R_ARM_CALL aux_arr_mul_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <mul_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_mul_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_vv
28: 000080e7 jalr ra # 24 <mul_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_intarr_floatarr+0x30>
riscv64#
0000000000000000 <mul_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_vv
28: 000080e7 jalr ra # 24 <mul_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_intarr_floatarr+0x30>
tricore#
00000000 <mul_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <mul_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_int_float_vv
24: 1d 00 00 00 j 24 <mul_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <mul_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_mul_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <mul_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <mul_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <mul_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <mul_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <mul_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_mul_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
mul_intarr_float#
STENCIL void mul_intarr_float(void) {
// Element-wise mul of int array and float scalar
aux_arr_mul_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_intarr_float>
28: R_AARCH64_CALL26 aux_arr_mul_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <mul_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <mul_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <mul_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_intarr_float+0x34>
1c: ebfffffe bl 0 <mul_intarr_float>
1c: R_ARM_CALL aux_arr_mul_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <mul_intarr_float>
2c: R_ARM_CALL aux_arr_mul_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_intarr_float+0x28>)
10: f7ff fffe bl 0 <mul_intarr_float>
10: R_ARM_THM_CALL aux_arr_mul_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <mul_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <mul_intarr_float>
10: R_ARM_THM_CALL aux_arr_mul_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <mul_intarr_float>
28: R_ARM_THM_CALL aux_arr_mul_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_intarr_float+0x28>)
10: f7ff fffe bl 0 <mul_intarr_float>
10: R_ARM_THM_CALL aux_arr_mul_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <mul_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <mul_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_vs
28: 000080e7 jalr ra # 24 <mul_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_intarr_float+0x30>
riscv64#
0000000000000000 <mul_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <mul_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <mul_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_vs
28: 000080e7 jalr ra # 24 <mul_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_intarr_float+0x30>
tricore#
00000000 <mul_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <mul_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <mul_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_mul_int_float_vs
26: 1d 00 00 00 j 26 <mul_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_mul_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <mul_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <mul_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <mul_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <mul_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_mul_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
mul_int_floatarr#
STENCIL void mul_int_floatarr(void) {
// Element-wise mul of int scalar and float array
aux_arr_mul_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <mul_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_mul_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <mul_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <mul_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <mul_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <mul_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <mul_int_floatarr>
1c: R_ARM_CALL aux_arr_mul_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <mul_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <mul_int_floatarr>
2c: R_ARM_CALL aux_arr_mul_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_floatarr>
e: R_ARM_THM_CALL aux_arr_mul_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <mul_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_floatarr>
e: R_ARM_THM_CALL aux_arr_mul_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <mul_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <mul_int_floatarr>
26: R_ARM_THM_CALL aux_arr_mul_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <mul_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <mul_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <mul_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <mul_int_floatarr>
e: R_ARM_THM_CALL aux_arr_mul_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <mul_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <mul_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_sv
28: 000080e7 jalr ra # 24 <mul_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_int_floatarr+0x30>
riscv64#
0000000000000000 <mul_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <mul_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_int_float_sv
28: 000080e7 jalr ra # 24 <mul_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_int_floatarr+0x30>
tricore#
00000000 <mul_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <mul_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_int_float_sv
24: 1d 00 00 00 j 24 <mul_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_mul_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <mul_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <mul_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <mul_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <mul_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_mul_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
mul_floatarr_intarr#
STENCIL void mul_floatarr_intarr(void) {
// Element-wise mul of float array and int array
aux_arr_mul_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_mul_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <mul_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <mul_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <mul_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <mul_floatarr_intarr+0x30>
18: ebfffffe bl 0 <mul_floatarr_intarr>
18: R_ARM_CALL aux_arr_mul_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <mul_floatarr_intarr>
28: R_ARM_CALL aux_arr_mul_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <mul_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_mul_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_mul_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_vv
28: 000080e7 jalr ra # 24 <mul_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_intarr+0x30>
riscv64#
0000000000000000 <mul_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_vv
28: 000080e7 jalr ra # 24 <mul_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_intarr+0x30>
tricore#
00000000 <mul_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <mul_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_float_int_vv
24: 1d 00 00 00 j 24 <mul_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <mul_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_mul_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <mul_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <mul_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <mul_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <mul_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <mul_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_mul_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
mul_floatarr_int#
STENCIL void mul_floatarr_int(void) {
// Element-wise mul of float array and int scalar
aux_arr_mul_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_mul_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <mul_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <mul_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <mul_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_floatarr_int+0x34>
1c: ebfffffe bl 0 <mul_floatarr_int>
1c: R_ARM_CALL aux_arr_mul_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <mul_floatarr_int>
2c: R_ARM_CALL aux_arr_mul_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_floatarr_int+0x28>)
e: f7ff fffe bl 0 <mul_floatarr_int>
e: R_ARM_THM_CALL aux_arr_mul_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <mul_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <mul_floatarr_int>
e: R_ARM_THM_CALL aux_arr_mul_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <mul_floatarr_int>
26: R_ARM_THM_CALL aux_arr_mul_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <mul_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <mul_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <mul_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_floatarr_int+0x28>)
e: f7ff fffe bl 0 <mul_floatarr_int>
e: R_ARM_THM_CALL aux_arr_mul_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <mul_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_vs
28: 000080e7 jalr ra # 24 <mul_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_int+0x30>
riscv64#
0000000000000000 <mul_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <mul_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_vs
28: 000080e7 jalr ra # 24 <mul_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_int+0x30>
tricore#
00000000 <mul_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_mul_float_int_vs
24: 1d 00 00 00 j 24 <mul_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_mul_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <mul_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <mul_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <mul_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <mul_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_mul_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
mul_float_intarr#
STENCIL void mul_float_intarr(void) {
// Element-wise mul of float scalar and int array
aux_arr_mul_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <mul_float_intarr>
28: R_AARCH64_CALL26 aux_arr_mul_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <mul_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <mul_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <mul_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_float_intarr+0x34>
1c: ebfffffe bl 0 <mul_float_intarr>
1c: R_ARM_CALL aux_arr_mul_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <mul_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <mul_float_intarr>
2c: R_ARM_CALL aux_arr_mul_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_float_intarr+0x28>)
10: f7ff fffe bl 0 <mul_float_intarr>
10: R_ARM_THM_CALL aux_arr_mul_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <mul_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <mul_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <mul_float_intarr>
10: R_ARM_THM_CALL aux_arr_mul_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <mul_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <mul_float_intarr>
28: R_ARM_THM_CALL aux_arr_mul_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_float_intarr+0x28>)
10: f7ff fffe bl 0 <mul_float_intarr>
10: R_ARM_THM_CALL aux_arr_mul_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <mul_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <mul_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <mul_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_sv
28: 000080e7 jalr ra # 24 <mul_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_float_intarr+0x30>
riscv64#
0000000000000000 <mul_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <mul_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <mul_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_int_sv
28: 000080e7 jalr ra # 24 <mul_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_float_intarr+0x30>
tricore#
00000000 <mul_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <mul_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <mul_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_mul_float_int_sv
26: 1d 00 00 00 j 26 <mul_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_mul_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <mul_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <mul_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <mul_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <mul_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_mul_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
mul_floatarr_floatarr#
STENCIL void mul_floatarr_floatarr(void) {
// Element-wise mul of float array and float array
aux_arr_mul_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_mul_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <mul_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <mul_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <mul_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <mul_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <mul_floatarr_floatarr>
18: R_ARM_CALL aux_arr_mul_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <mul_floatarr_floatarr>
28: R_ARM_CALL aux_arr_mul_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <mul_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_mul_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <mul_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <mul_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <mul_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <mul_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <mul_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_mul_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <mul_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_vv
28: 000080e7 jalr ra # 24 <mul_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <mul_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <mul_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_vv
28: 000080e7 jalr ra # 24 <mul_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_floatarr+0x30>
tricore#
00000000 <mul_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <mul_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <mul_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <mul_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_mul_float_float_vv
24: 1d 00 00 00 j 24 <mul_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <mul_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_mul_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <mul_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <mul_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <mul_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <mul_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <mul_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_mul_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
mul_floatarr_float#
STENCIL void mul_floatarr_float(void) {
// Element-wise mul of float array and float scalar
aux_arr_mul_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <mul_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_mul_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <mul_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <mul_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <mul_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_floatarr_float+0x34>
1c: ebfffffe bl 0 <mul_floatarr_float>
1c: R_ARM_CALL aux_arr_mul_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <mul_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <mul_floatarr_float>
2c: R_ARM_CALL aux_arr_mul_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_floatarr_float+0x28>)
10: f7ff fffe bl 0 <mul_floatarr_float>
10: R_ARM_THM_CALL aux_arr_mul_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <mul_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <mul_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <mul_floatarr_float>
10: R_ARM_THM_CALL aux_arr_mul_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <mul_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <mul_floatarr_float>
28: R_ARM_THM_CALL aux_arr_mul_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_floatarr_float+0x28>)
10: f7ff fffe bl 0 <mul_floatarr_float>
10: R_ARM_THM_CALL aux_arr_mul_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <mul_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <mul_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <mul_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_vs
28: 000080e7 jalr ra # 24 <mul_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_float+0x30>
riscv64#
0000000000000000 <mul_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <mul_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <mul_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_vs
28: 000080e7 jalr ra # 24 <mul_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_floatarr_float+0x30>
tricore#
00000000 <mul_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <mul_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <mul_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_mul_float_float_vs
26: 1d 00 00 00 j 26 <mul_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_mul_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <mul_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <mul_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <mul_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <mul_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_mul_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
mul_float_floatarr#
STENCIL void mul_float_floatarr(void) {
// Element-wise mul of float scalar and float array
aux_arr_mul_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <mul_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <mul_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_mul_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <mul_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <mul_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <mul_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <mul_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <mul_float_floatarr+0x34>
1c: ebfffffe bl 0 <mul_float_floatarr>
1c: R_ARM_CALL aux_arr_mul_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <mul_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <mul_float_floatarr>
2c: R_ARM_CALL aux_arr_mul_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <mul_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_float_floatarr+0x28>)
10: f7ff fffe bl 0 <mul_float_floatarr>
10: R_ARM_THM_CALL aux_arr_mul_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <mul_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <mul_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <mul_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <mul_float_floatarr>
10: R_ARM_THM_CALL aux_arr_mul_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <mul_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <mul_float_floatarr>
28: R_ARM_THM_CALL aux_arr_mul_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <mul_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <mul_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <mul_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <mul_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <mul_float_floatarr+0x28>)
10: f7ff fffe bl 0 <mul_float_floatarr>
10: R_ARM_THM_CALL aux_arr_mul_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <mul_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <mul_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <mul_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_sv
28: 000080e7 jalr ra # 24 <mul_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_float_floatarr+0x30>
riscv64#
0000000000000000 <mul_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <mul_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <mul_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_mul_float_float_sv
28: 000080e7 jalr ra # 24 <mul_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <mul_float_floatarr+0x30>
tricore#
00000000 <mul_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <mul_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <mul_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <mul_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <mul_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <mul_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_mul_float_float_sv
26: 1d 00 00 00 j 26 <mul_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <mul_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <mul_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_mul_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <mul_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <mul_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <mul_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <mul_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <mul_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <mul_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <mul_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_mul_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
div_intarr_intarr#
STENCIL void div_intarr_intarr(void) {
// Element-wise div of int array and int array
aux_arr_div_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_div_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <div_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <div_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <div_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <div_intarr_intarr+0x30>
18: ebfffffe bl 0 <div_intarr_intarr>
18: R_ARM_CALL aux_arr_div_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <div_intarr_intarr>
28: R_ARM_CALL aux_arr_div_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <div_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_div_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_vv
28: 000080e7 jalr ra # 24 <div_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_intarr+0x30>
riscv64#
0000000000000000 <div_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_vv
28: 000080e7 jalr ra # 24 <div_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_intarr+0x30>
tricore#
00000000 <div_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <div_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_div_int_int_vv
24: 1d 00 00 00 j 24 <div_intarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <div_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_div_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <div_intarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <div_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <div_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <div_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <div_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_div_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
div_intarr_int#
STENCIL void div_intarr_int(void) {
// Element-wise div of int array and int scalar
aux_arr_div_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_intarr_int>
28: R_AARCH64_CALL26 aux_arr_div_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <div_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <div_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <div_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_intarr_int+0x34>
1c: ebfffffe bl 0 <div_intarr_int>
1c: R_ARM_CALL aux_arr_div_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <div_intarr_int>
2c: R_ARM_CALL aux_arr_div_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <div_intarr_int+0x28>)
e: f7ff fffe bl 0 <div_intarr_int>
e: R_ARM_THM_CALL aux_arr_div_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <div_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <div_intarr_int>
e: R_ARM_THM_CALL aux_arr_div_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <div_intarr_int>
26: R_ARM_THM_CALL aux_arr_div_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <div_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <div_intarr_int+0x28>)
e: f7ff fffe bl 0 <div_intarr_int>
e: R_ARM_THM_CALL aux_arr_div_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <div_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_vs
28: 000080e7 jalr ra # 24 <div_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_int+0x30>
riscv64#
0000000000000000 <div_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <div_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_vs
28: 000080e7 jalr ra # 24 <div_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_int+0x30>
tricore#
00000000 <div_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_div_int_int_vs
24: 1d 00 00 00 j 24 <div_intarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_div_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_intarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <div_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <div_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <div_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <div_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_div_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
div_int_intarr#
STENCIL void div_int_intarr(void) {
// Element-wise div of int scalar and int array
aux_arr_div_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <div_int_intarr>
28: R_AARCH64_CALL26 aux_arr_div_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <div_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <div_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <div_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <div_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <div_int_intarr>
1c: R_ARM_CALL aux_arr_div_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <div_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <div_int_intarr>
2c: R_ARM_CALL aux_arr_div_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_intarr>
e: R_ARM_THM_CALL aux_arr_div_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <div_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_intarr>
e: R_ARM_THM_CALL aux_arr_div_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <div_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <div_int_intarr>
26: R_ARM_THM_CALL aux_arr_div_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <div_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_intarr>
e: R_ARM_THM_CALL aux_arr_div_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <div_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <div_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_sv
28: 000080e7 jalr ra # 24 <div_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_int_intarr+0x30>
riscv64#
0000000000000000 <div_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <div_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_int_sv
28: 000080e7 jalr ra # 24 <div_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_int_intarr+0x30>
tricore#
00000000 <div_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <div_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_div_int_int_sv
24: 1d 00 00 00 j 24 <div_int_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_div_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_int_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <div_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <div_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <div_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <div_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_div_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
div_intarr_floatarr#
STENCIL void div_intarr_floatarr(void) {
// Element-wise div of int array and float array
aux_arr_div_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_div_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <div_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <div_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <div_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <div_intarr_floatarr+0x30>
18: ebfffffe bl 0 <div_intarr_floatarr>
18: R_ARM_CALL aux_arr_div_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <div_intarr_floatarr>
28: R_ARM_CALL aux_arr_div_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <div_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_div_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_vv
28: 000080e7 jalr ra # 24 <div_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_floatarr+0x30>
riscv64#
0000000000000000 <div_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_vv
28: 000080e7 jalr ra # 24 <div_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_floatarr+0x30>
tricore#
00000000 <div_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <div_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_div_int_float_vv
24: 1d 00 00 00 j 24 <div_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <div_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_div_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <div_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <div_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <div_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <div_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <div_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_div_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
div_intarr_float#
STENCIL void div_intarr_float(void) {
// Element-wise div of int array and float scalar
aux_arr_div_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_intarr_float>
28: R_AARCH64_CALL26 aux_arr_div_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <div_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <div_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <div_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_intarr_float+0x34>
1c: ebfffffe bl 0 <div_intarr_float>
1c: R_ARM_CALL aux_arr_div_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <div_intarr_float>
2c: R_ARM_CALL aux_arr_div_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_intarr_float+0x28>)
10: f7ff fffe bl 0 <div_intarr_float>
10: R_ARM_THM_CALL aux_arr_div_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <div_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <div_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <div_intarr_float>
10: R_ARM_THM_CALL aux_arr_div_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <div_intarr_float>
28: R_ARM_THM_CALL aux_arr_div_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_intarr_float+0x28>)
10: f7ff fffe bl 0 <div_intarr_float>
10: R_ARM_THM_CALL aux_arr_div_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <div_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <div_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_vs
28: 000080e7 jalr ra # 24 <div_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_float+0x30>
riscv64#
0000000000000000 <div_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <div_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <div_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_vs
28: 000080e7 jalr ra # 24 <div_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_intarr_float+0x30>
tricore#
00000000 <div_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <div_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <div_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <div_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <div_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_div_int_float_vs
26: 1d 00 00 00 j 26 <div_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_div_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <div_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <div_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <div_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <div_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_div_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
div_int_floatarr#
STENCIL void div_int_floatarr(void) {
// Element-wise div of int scalar and float array
aux_arr_div_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <div_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_div_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <div_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <div_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <div_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <div_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <div_int_floatarr>
1c: R_ARM_CALL aux_arr_div_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <div_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <div_int_floatarr>
2c: R_ARM_CALL aux_arr_div_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_floatarr>
e: R_ARM_THM_CALL aux_arr_div_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <div_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_floatarr>
e: R_ARM_THM_CALL aux_arr_div_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <div_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <div_int_floatarr>
26: R_ARM_THM_CALL aux_arr_div_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <div_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <div_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <div_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <div_int_floatarr>
e: R_ARM_THM_CALL aux_arr_div_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <div_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <div_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_sv
28: 000080e7 jalr ra # 24 <div_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_int_floatarr+0x30>
riscv64#
0000000000000000 <div_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <div_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_int_float_sv
28: 000080e7 jalr ra # 24 <div_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_int_floatarr+0x30>
tricore#
00000000 <div_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <div_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_div_int_float_sv
24: 1d 00 00 00 j 24 <div_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_div_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <div_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <div_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <div_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <div_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_div_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
div_floatarr_intarr#
STENCIL void div_floatarr_intarr(void) {
// Element-wise div of float array and int array
aux_arr_div_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_div_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <div_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <div_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <div_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <div_floatarr_intarr+0x30>
18: ebfffffe bl 0 <div_floatarr_intarr>
18: R_ARM_CALL aux_arr_div_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <div_floatarr_intarr>
28: R_ARM_CALL aux_arr_div_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <div_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_div_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_div_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_vv
28: 000080e7 jalr ra # 24 <div_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_intarr+0x30>
riscv64#
0000000000000000 <div_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_vv
28: 000080e7 jalr ra # 24 <div_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_intarr+0x30>
tricore#
00000000 <div_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <div_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_div_float_int_vv
24: 1d 00 00 00 j 24 <div_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <div_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_div_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <div_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <div_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <div_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <div_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <div_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_div_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
div_floatarr_int#
STENCIL void div_floatarr_int(void) {
// Element-wise div of float array and int scalar
aux_arr_div_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_div_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <div_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <div_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <div_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_floatarr_int+0x34>
1c: ebfffffe bl 0 <div_floatarr_int>
1c: R_ARM_CALL aux_arr_div_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <div_floatarr_int>
2c: R_ARM_CALL aux_arr_div_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <div_floatarr_int+0x28>)
e: f7ff fffe bl 0 <div_floatarr_int>
e: R_ARM_THM_CALL aux_arr_div_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <div_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <div_floatarr_int>
e: R_ARM_THM_CALL aux_arr_div_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <div_floatarr_int>
26: R_ARM_THM_CALL aux_arr_div_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <div_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <div_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <div_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <div_floatarr_int+0x28>)
e: f7ff fffe bl 0 <div_floatarr_int>
e: R_ARM_THM_CALL aux_arr_div_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <div_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_vs
28: 000080e7 jalr ra # 24 <div_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_int+0x30>
riscv64#
0000000000000000 <div_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <div_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_vs
28: 000080e7 jalr ra # 24 <div_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_int+0x30>
tricore#
00000000 <div_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_div_float_int_vs
24: 1d 00 00 00 j 24 <div_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_div_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <div_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <div_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <div_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <div_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_div_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
div_float_intarr#
STENCIL void div_float_intarr(void) {
// Element-wise div of float scalar and int array
aux_arr_div_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <div_float_intarr>
28: R_AARCH64_CALL26 aux_arr_div_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <div_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <div_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <div_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_float_intarr+0x34>
1c: ebfffffe bl 0 <div_float_intarr>
1c: R_ARM_CALL aux_arr_div_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <div_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <div_float_intarr>
2c: R_ARM_CALL aux_arr_div_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_float_intarr+0x28>)
10: f7ff fffe bl 0 <div_float_intarr>
10: R_ARM_THM_CALL aux_arr_div_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <div_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <div_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <div_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <div_float_intarr>
10: R_ARM_THM_CALL aux_arr_div_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <div_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <div_float_intarr>
28: R_ARM_THM_CALL aux_arr_div_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_float_intarr+0x28>)
10: f7ff fffe bl 0 <div_float_intarr>
10: R_ARM_THM_CALL aux_arr_div_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <div_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <div_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <div_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_sv
28: 000080e7 jalr ra # 24 <div_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_float_intarr+0x30>
riscv64#
0000000000000000 <div_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <div_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <div_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_int_sv
28: 000080e7 jalr ra # 24 <div_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_float_intarr+0x30>
tricore#
00000000 <div_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <div_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <div_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <div_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <div_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_div_float_int_sv
26: 1d 00 00 00 j 26 <div_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_div_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <div_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <div_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <div_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <div_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_div_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
div_floatarr_floatarr#
STENCIL void div_floatarr_floatarr(void) {
// Element-wise div of float array and float array
aux_arr_div_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_div_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <div_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <div_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <div_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <div_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <div_floatarr_floatarr>
18: R_ARM_CALL aux_arr_div_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <div_floatarr_floatarr>
28: R_ARM_CALL aux_arr_div_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <div_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_div_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <div_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <div_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <div_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <div_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <div_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_div_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <div_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_vv
28: 000080e7 jalr ra # 24 <div_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <div_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <div_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_vv
28: 000080e7 jalr ra # 24 <div_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_floatarr+0x30>
tricore#
00000000 <div_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <div_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <div_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <div_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <div_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <div_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_div_float_float_vv
24: 1d 00 00 00 j 24 <div_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <div_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_div_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <div_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <div_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <div_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <div_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <div_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_div_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
div_floatarr_float#
STENCIL void div_floatarr_float(void) {
// Element-wise div of float array and float scalar
aux_arr_div_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <div_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_div_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <div_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <div_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <div_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_floatarr_float+0x34>
1c: ebfffffe bl 0 <div_floatarr_float>
1c: R_ARM_CALL aux_arr_div_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <div_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <div_floatarr_float>
2c: R_ARM_CALL aux_arr_div_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_floatarr_float+0x28>)
10: f7ff fffe bl 0 <div_floatarr_float>
10: R_ARM_THM_CALL aux_arr_div_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <div_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <div_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <div_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <div_floatarr_float>
10: R_ARM_THM_CALL aux_arr_div_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <div_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <div_floatarr_float>
28: R_ARM_THM_CALL aux_arr_div_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_floatarr_float+0x28>)
10: f7ff fffe bl 0 <div_floatarr_float>
10: R_ARM_THM_CALL aux_arr_div_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <div_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <div_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <div_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_vs
28: 000080e7 jalr ra # 24 <div_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_float+0x30>
riscv64#
0000000000000000 <div_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <div_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <div_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_vs
28: 000080e7 jalr ra # 24 <div_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_floatarr_float+0x30>
tricore#
00000000 <div_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <div_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <div_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <div_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <div_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_div_float_float_vs
26: 1d 00 00 00 j 26 <div_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_div_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <div_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <div_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <div_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <div_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_div_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
div_float_floatarr#
STENCIL void div_float_floatarr(void) {
// Element-wise div of float scalar and float array
aux_arr_div_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <div_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <div_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_div_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <div_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <div_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <div_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <div_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <div_float_floatarr+0x34>
1c: ebfffffe bl 0 <div_float_floatarr>
1c: R_ARM_CALL aux_arr_div_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <div_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <div_float_floatarr>
2c: R_ARM_CALL aux_arr_div_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <div_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_float_floatarr+0x28>)
10: f7ff fffe bl 0 <div_float_floatarr>
10: R_ARM_THM_CALL aux_arr_div_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <div_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <div_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <div_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <div_float_floatarr>
10: R_ARM_THM_CALL aux_arr_div_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <div_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <div_float_floatarr>
28: R_ARM_THM_CALL aux_arr_div_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <div_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <div_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <div_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <div_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <div_float_floatarr+0x28>)
10: f7ff fffe bl 0 <div_float_floatarr>
10: R_ARM_THM_CALL aux_arr_div_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <div_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <div_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <div_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_sv
28: 000080e7 jalr ra # 24 <div_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_float_floatarr+0x30>
riscv64#
0000000000000000 <div_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <div_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <div_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_div_float_float_sv
28: 000080e7 jalr ra # 24 <div_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <div_float_floatarr+0x30>
tricore#
00000000 <div_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <div_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <div_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <div_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <div_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <div_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_div_float_float_sv
26: 1d 00 00 00 j 26 <div_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <div_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <div_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_div_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <div_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <div_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <div_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <div_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <div_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <div_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <div_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_div_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
min_intarr_intarr#
STENCIL void min_intarr_intarr(void) {
// Element-wise min of int array and int array
aux_arr_min_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <min_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_min_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <min_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <min_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <min_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <min_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <min_intarr_intarr+0x30>
18: ebfffffe bl 0 <min_intarr_intarr>
18: R_ARM_CALL aux_arr_min_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <min_intarr_intarr>
28: R_ARM_CALL aux_arr_min_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <min_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <min_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_min_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <min_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_vv
28: 000080e7 jalr ra # 24 <min_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_intarr_intarr+0x30>
riscv64#
0000000000000000 <min_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_vv
28: 000080e7 jalr ra # 24 <min_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_intarr_intarr+0x30>
tricore#
00000000 <min_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <min_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_min_int_int_vv
24: 1d 00 00 00 j 24 <min_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <min_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <min_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_min_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <min_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <min_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <min_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <min_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <min_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <min_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_min_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
min_intarr_int#
STENCIL void min_intarr_int(void) {
// Element-wise min of int array and int scalar
aux_arr_min_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <min_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_intarr_int>
28: R_AARCH64_CALL26 aux_arr_min_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <min_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <min_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <min_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <min_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_intarr_int+0x34>
1c: ebfffffe bl 0 <min_intarr_int>
1c: R_ARM_CALL aux_arr_min_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <min_intarr_int>
2c: R_ARM_CALL aux_arr_min_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <min_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <min_intarr_int+0x28>)
e: f7ff fffe bl 0 <min_intarr_int>
e: R_ARM_THM_CALL aux_arr_min_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <min_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <min_intarr_int>
e: R_ARM_THM_CALL aux_arr_min_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <min_intarr_int>
26: R_ARM_THM_CALL aux_arr_min_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <min_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <min_intarr_int+0x28>)
e: f7ff fffe bl 0 <min_intarr_int>
e: R_ARM_THM_CALL aux_arr_min_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <min_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_vs
28: 000080e7 jalr ra # 24 <min_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_intarr_int+0x30>
riscv64#
0000000000000000 <min_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <min_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_vs
28: 000080e7 jalr ra # 24 <min_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_intarr_int+0x30>
tricore#
00000000 <min_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_min_int_int_vs
24: 1d 00 00 00 j 24 <min_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <min_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_min_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <min_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <min_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <min_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <min_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <min_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_min_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
min_int_intarr#
STENCIL void min_int_intarr(void) {
// Element-wise min of int scalar and int array
aux_arr_min_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <min_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <min_int_intarr>
28: R_AARCH64_CALL26 aux_arr_min_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <min_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <min_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <min_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <min_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <min_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <min_int_intarr>
1c: R_ARM_CALL aux_arr_min_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <min_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <min_int_intarr>
2c: R_ARM_CALL aux_arr_min_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <min_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_intarr>
e: R_ARM_THM_CALL aux_arr_min_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <min_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_intarr>
e: R_ARM_THM_CALL aux_arr_min_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <min_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <min_int_intarr>
26: R_ARM_THM_CALL aux_arr_min_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <min_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_intarr>
e: R_ARM_THM_CALL aux_arr_min_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <min_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <min_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_sv
28: 000080e7 jalr ra # 24 <min_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_int_intarr+0x30>
riscv64#
0000000000000000 <min_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <min_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_int_sv
28: 000080e7 jalr ra # 24 <min_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <min_int_intarr+0x30>
tricore#
00000000 <min_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <min_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_min_int_int_sv
24: 1d 00 00 00 j 24 <min_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <min_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_min_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <min_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <min_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <min_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <min_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <min_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_min_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
min_intarr_floatarr#
STENCIL void min_intarr_floatarr(void) {
// Element-wise min of int array and float array
aux_arr_min_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_min_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <min_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <min_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <min_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <min_intarr_floatarr+0x30>
18: ebfffffe bl 0 <min_intarr_floatarr>
18: R_ARM_CALL aux_arr_min_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <min_intarr_floatarr>
28: R_ARM_CALL aux_arr_min_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <min_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_min_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_vv
28: 000080e7 jalr ra # 24 <min_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_intarr_floatarr+0x30>
riscv64#
0000000000000000 <min_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_vv
28: 000080e7 jalr ra # 24 <min_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_intarr_floatarr+0x30>
tricore#
00000000 <min_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <min_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_min_int_float_vv
24: 1d 00 00 00 j 24 <min_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <min_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_min_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <min_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <min_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <min_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <min_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <min_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_min_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
min_intarr_float#
STENCIL void min_intarr_float(void) {
// Element-wise min of int array and float scalar
aux_arr_min_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_intarr_float>
28: R_AARCH64_CALL26 aux_arr_min_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <min_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <min_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <min_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_intarr_float+0x34>
1c: ebfffffe bl 0 <min_intarr_float>
1c: R_ARM_CALL aux_arr_min_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <min_intarr_float>
2c: R_ARM_CALL aux_arr_min_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_intarr_float+0x28>)
10: f7ff fffe bl 0 <min_intarr_float>
10: R_ARM_THM_CALL aux_arr_min_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <min_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <min_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <min_intarr_float>
10: R_ARM_THM_CALL aux_arr_min_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <min_intarr_float>
28: R_ARM_THM_CALL aux_arr_min_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_intarr_float+0x28>)
10: f7ff fffe bl 0 <min_intarr_float>
10: R_ARM_THM_CALL aux_arr_min_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <min_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <min_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_vs
28: 000080e7 jalr ra # 24 <min_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_intarr_float+0x30>
riscv64#
0000000000000000 <min_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <min_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <min_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_vs
28: 000080e7 jalr ra # 24 <min_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_intarr_float+0x30>
tricore#
00000000 <min_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <min_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <min_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <min_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <min_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_min_int_float_vs
26: 1d 00 00 00 j 26 <min_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_min_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <min_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <min_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <min_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <min_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_min_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
min_int_floatarr#
STENCIL void min_int_floatarr(void) {
// Element-wise min of int scalar and float array
aux_arr_min_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <min_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_min_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <min_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <min_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <min_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <min_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <min_int_floatarr>
1c: R_ARM_CALL aux_arr_min_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <min_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <min_int_floatarr>
2c: R_ARM_CALL aux_arr_min_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_floatarr>
e: R_ARM_THM_CALL aux_arr_min_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <min_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_floatarr>
e: R_ARM_THM_CALL aux_arr_min_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <min_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <min_int_floatarr>
26: R_ARM_THM_CALL aux_arr_min_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <min_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <min_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <min_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <min_int_floatarr>
e: R_ARM_THM_CALL aux_arr_min_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <min_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <min_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_sv
28: 000080e7 jalr ra # 24 <min_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_int_floatarr+0x30>
riscv64#
0000000000000000 <min_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <min_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_int_float_sv
28: 000080e7 jalr ra # 24 <min_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_int_floatarr+0x30>
tricore#
00000000 <min_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <min_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_min_int_float_sv
24: 1d 00 00 00 j 24 <min_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_min_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <min_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <min_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <min_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <min_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_min_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
min_floatarr_intarr#
STENCIL void min_floatarr_intarr(void) {
// Element-wise min of float array and int array
aux_arr_min_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_min_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <min_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <min_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <min_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <min_floatarr_intarr+0x30>
18: ebfffffe bl 0 <min_floatarr_intarr>
18: R_ARM_CALL aux_arr_min_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <min_floatarr_intarr>
28: R_ARM_CALL aux_arr_min_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <min_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_min_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_min_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_vv
28: 000080e7 jalr ra # 24 <min_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_intarr+0x30>
riscv64#
0000000000000000 <min_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_vv
28: 000080e7 jalr ra # 24 <min_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_intarr+0x30>
tricore#
00000000 <min_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <min_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_min_float_int_vv
24: 1d 00 00 00 j 24 <min_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <min_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_min_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <min_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <min_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <min_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <min_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <min_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_min_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
min_floatarr_int#
STENCIL void min_floatarr_int(void) {
// Element-wise min of float array and int scalar
aux_arr_min_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_min_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <min_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <min_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <min_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_floatarr_int+0x34>
1c: ebfffffe bl 0 <min_floatarr_int>
1c: R_ARM_CALL aux_arr_min_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <min_floatarr_int>
2c: R_ARM_CALL aux_arr_min_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <min_floatarr_int+0x28>)
e: f7ff fffe bl 0 <min_floatarr_int>
e: R_ARM_THM_CALL aux_arr_min_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <min_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <min_floatarr_int>
e: R_ARM_THM_CALL aux_arr_min_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <min_floatarr_int>
26: R_ARM_THM_CALL aux_arr_min_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <min_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <min_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <min_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <min_floatarr_int+0x28>)
e: f7ff fffe bl 0 <min_floatarr_int>
e: R_ARM_THM_CALL aux_arr_min_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <min_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_vs
28: 000080e7 jalr ra # 24 <min_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_int+0x30>
riscv64#
0000000000000000 <min_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <min_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_vs
28: 000080e7 jalr ra # 24 <min_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_int+0x30>
tricore#
00000000 <min_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_min_float_int_vs
24: 1d 00 00 00 j 24 <min_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_min_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <min_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <min_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <min_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <min_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_min_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
min_float_intarr#
STENCIL void min_float_intarr(void) {
// Element-wise min of float scalar and int array
aux_arr_min_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <min_float_intarr>
28: R_AARCH64_CALL26 aux_arr_min_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <min_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <min_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <min_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_float_intarr+0x34>
1c: ebfffffe bl 0 <min_float_intarr>
1c: R_ARM_CALL aux_arr_min_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <min_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <min_float_intarr>
2c: R_ARM_CALL aux_arr_min_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_float_intarr+0x28>)
10: f7ff fffe bl 0 <min_float_intarr>
10: R_ARM_THM_CALL aux_arr_min_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <min_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <min_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <min_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <min_float_intarr>
10: R_ARM_THM_CALL aux_arr_min_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <min_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <min_float_intarr>
28: R_ARM_THM_CALL aux_arr_min_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_float_intarr+0x28>)
10: f7ff fffe bl 0 <min_float_intarr>
10: R_ARM_THM_CALL aux_arr_min_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <min_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <min_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <min_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_sv
28: 000080e7 jalr ra # 24 <min_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_float_intarr+0x30>
riscv64#
0000000000000000 <min_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <min_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <min_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_int_sv
28: 000080e7 jalr ra # 24 <min_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_float_intarr+0x30>
tricore#
00000000 <min_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <min_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <min_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <min_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <min_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_min_float_int_sv
26: 1d 00 00 00 j 26 <min_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_min_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <min_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <min_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <min_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <min_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_min_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
min_floatarr_floatarr#
STENCIL void min_floatarr_floatarr(void) {
// Element-wise min of float array and float array
aux_arr_min_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_min_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <min_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <min_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <min_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <min_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <min_floatarr_floatarr>
18: R_ARM_CALL aux_arr_min_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <min_floatarr_floatarr>
28: R_ARM_CALL aux_arr_min_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <min_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_min_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <min_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <min_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <min_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <min_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <min_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_min_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <min_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_vv
28: 000080e7 jalr ra # 24 <min_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <min_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <min_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_vv
28: 000080e7 jalr ra # 24 <min_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_floatarr+0x30>
tricore#
00000000 <min_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <min_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <min_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <min_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <min_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <min_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_min_float_float_vv
24: 1d 00 00 00 j 24 <min_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <min_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_min_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <min_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <min_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <min_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <min_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <min_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_min_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
min_floatarr_float#
STENCIL void min_floatarr_float(void) {
// Element-wise min of float array and float scalar
aux_arr_min_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <min_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_min_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <min_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <min_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <min_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_floatarr_float+0x34>
1c: ebfffffe bl 0 <min_floatarr_float>
1c: R_ARM_CALL aux_arr_min_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <min_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <min_floatarr_float>
2c: R_ARM_CALL aux_arr_min_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_floatarr_float+0x28>)
10: f7ff fffe bl 0 <min_floatarr_float>
10: R_ARM_THM_CALL aux_arr_min_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <min_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <min_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <min_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <min_floatarr_float>
10: R_ARM_THM_CALL aux_arr_min_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <min_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <min_floatarr_float>
28: R_ARM_THM_CALL aux_arr_min_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_floatarr_float+0x28>)
10: f7ff fffe bl 0 <min_floatarr_float>
10: R_ARM_THM_CALL aux_arr_min_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <min_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <min_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <min_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_vs
28: 000080e7 jalr ra # 24 <min_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_float+0x30>
riscv64#
0000000000000000 <min_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <min_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <min_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_vs
28: 000080e7 jalr ra # 24 <min_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_floatarr_float+0x30>
tricore#
00000000 <min_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <min_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <min_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <min_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <min_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_min_float_float_vs
26: 1d 00 00 00 j 26 <min_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_min_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <min_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <min_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <min_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <min_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_min_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
min_float_floatarr#
STENCIL void min_float_floatarr(void) {
// Element-wise min of float scalar and float array
aux_arr_min_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <min_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <min_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_min_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <min_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <min_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <min_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <min_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <min_float_floatarr+0x34>
1c: ebfffffe bl 0 <min_float_floatarr>
1c: R_ARM_CALL aux_arr_min_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <min_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <min_float_floatarr>
2c: R_ARM_CALL aux_arr_min_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <min_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_float_floatarr+0x28>)
10: f7ff fffe bl 0 <min_float_floatarr>
10: R_ARM_THM_CALL aux_arr_min_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <min_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <min_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <min_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <min_float_floatarr>
10: R_ARM_THM_CALL aux_arr_min_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <min_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <min_float_floatarr>
28: R_ARM_THM_CALL aux_arr_min_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <min_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <min_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <min_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <min_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <min_float_floatarr+0x28>)
10: f7ff fffe bl 0 <min_float_floatarr>
10: R_ARM_THM_CALL aux_arr_min_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <min_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <min_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <min_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_sv
28: 000080e7 jalr ra # 24 <min_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_float_floatarr+0x30>
riscv64#
0000000000000000 <min_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <min_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <min_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_min_float_float_sv
28: 000080e7 jalr ra # 24 <min_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <min_float_floatarr+0x30>
tricore#
00000000 <min_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <min_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <min_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <min_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <min_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <min_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_min_float_float_sv
26: 1d 00 00 00 j 26 <min_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <min_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <min_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_min_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <min_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <min_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <min_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <min_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <min_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <min_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <min_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_min_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
max_intarr_intarr#
STENCIL void max_intarr_intarr(void) {
// Element-wise max of int array and int array
aux_arr_max_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <max_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_max_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <max_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <max_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <max_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <max_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <max_intarr_intarr+0x30>
18: ebfffffe bl 0 <max_intarr_intarr>
18: R_ARM_CALL aux_arr_max_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <max_intarr_intarr>
28: R_ARM_CALL aux_arr_max_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <max_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <max_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_max_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <max_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_vv
28: 000080e7 jalr ra # 24 <max_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_intarr_intarr+0x30>
riscv64#
0000000000000000 <max_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_vv
28: 000080e7 jalr ra # 24 <max_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_intarr_intarr+0x30>
tricore#
00000000 <max_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <max_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_max_int_int_vv
24: 1d 00 00 00 j 24 <max_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <max_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <max_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_max_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <max_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <max_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <max_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <max_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <max_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <max_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_max_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
max_intarr_int#
STENCIL void max_intarr_int(void) {
// Element-wise max of int array and int scalar
aux_arr_max_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <max_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_intarr_int>
28: R_AARCH64_CALL26 aux_arr_max_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <max_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <max_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <max_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <max_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_intarr_int+0x34>
1c: ebfffffe bl 0 <max_intarr_int>
1c: R_ARM_CALL aux_arr_max_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <max_intarr_int>
2c: R_ARM_CALL aux_arr_max_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <max_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <max_intarr_int+0x28>)
e: f7ff fffe bl 0 <max_intarr_int>
e: R_ARM_THM_CALL aux_arr_max_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <max_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <max_intarr_int>
e: R_ARM_THM_CALL aux_arr_max_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <max_intarr_int>
26: R_ARM_THM_CALL aux_arr_max_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <max_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <max_intarr_int+0x28>)
e: f7ff fffe bl 0 <max_intarr_int>
e: R_ARM_THM_CALL aux_arr_max_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <max_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_vs
28: 000080e7 jalr ra # 24 <max_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_intarr_int+0x30>
riscv64#
0000000000000000 <max_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <max_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_vs
28: 000080e7 jalr ra # 24 <max_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_intarr_int+0x30>
tricore#
00000000 <max_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_max_int_int_vs
24: 1d 00 00 00 j 24 <max_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <max_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_max_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <max_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <max_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <max_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <max_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <max_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_max_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
max_int_intarr#
STENCIL void max_int_intarr(void) {
// Element-wise max of int scalar and int array
aux_arr_max_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <max_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <max_int_intarr>
28: R_AARCH64_CALL26 aux_arr_max_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <max_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <max_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <max_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <max_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <max_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <max_int_intarr>
1c: R_ARM_CALL aux_arr_max_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <max_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <max_int_intarr>
2c: R_ARM_CALL aux_arr_max_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <max_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_intarr>
e: R_ARM_THM_CALL aux_arr_max_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <max_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_intarr>
e: R_ARM_THM_CALL aux_arr_max_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <max_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <max_int_intarr>
26: R_ARM_THM_CALL aux_arr_max_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <max_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_intarr>
e: R_ARM_THM_CALL aux_arr_max_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <max_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <max_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_sv
28: 000080e7 jalr ra # 24 <max_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_int_intarr+0x30>
riscv64#
0000000000000000 <max_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <max_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_int_sv
28: 000080e7 jalr ra # 24 <max_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <max_int_intarr+0x30>
tricore#
00000000 <max_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <max_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_max_int_int_sv
24: 1d 00 00 00 j 24 <max_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <max_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_max_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <max_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <max_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <max_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <max_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <max_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_max_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
max_intarr_floatarr#
STENCIL void max_intarr_floatarr(void) {
// Element-wise max of int array and float array
aux_arr_max_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_max_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <max_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <max_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <max_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <max_intarr_floatarr+0x30>
18: ebfffffe bl 0 <max_intarr_floatarr>
18: R_ARM_CALL aux_arr_max_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <max_intarr_floatarr>
28: R_ARM_CALL aux_arr_max_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <max_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_max_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_vv
28: 000080e7 jalr ra # 24 <max_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_intarr_floatarr+0x30>
riscv64#
0000000000000000 <max_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_vv
28: 000080e7 jalr ra # 24 <max_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_intarr_floatarr+0x30>
tricore#
00000000 <max_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <max_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_max_int_float_vv
24: 1d 00 00 00 j 24 <max_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <max_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_max_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <max_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <max_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <max_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <max_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <max_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_max_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
max_intarr_float#
STENCIL void max_intarr_float(void) {
// Element-wise max of int array and float scalar
aux_arr_max_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_intarr_float>
28: R_AARCH64_CALL26 aux_arr_max_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_intarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <max_intarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <max_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <max_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_intarr_float+0x34>
1c: ebfffffe bl 0 <max_intarr_float>
1c: R_ARM_CALL aux_arr_max_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <max_intarr_float>
2c: R_ARM_CALL aux_arr_max_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_intarr_float+0x28>)
10: f7ff fffe bl 0 <max_intarr_float>
10: R_ARM_THM_CALL aux_arr_max_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <max_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <max_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <max_intarr_float>
10: R_ARM_THM_CALL aux_arr_max_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <max_intarr_float>
28: R_ARM_THM_CALL aux_arr_max_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_intarr_float+0x28>)
10: f7ff fffe bl 0 <max_intarr_float>
10: R_ARM_THM_CALL aux_arr_max_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <max_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <max_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_vs
28: 000080e7 jalr ra # 24 <max_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_intarr_float+0x30>
riscv64#
0000000000000000 <max_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <max_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <max_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_vs
28: 000080e7 jalr ra # 24 <max_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_intarr_float+0x30>
tricore#
00000000 <max_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <max_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <max_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <max_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <max_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_max_int_float_vs
26: 1d 00 00 00 j 26 <max_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_max_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <max_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <max_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <max_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <max_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_max_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
max_int_floatarr#
STENCIL void max_int_floatarr(void) {
// Element-wise max of int scalar and float array
aux_arr_max_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <max_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_max_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <max_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <max_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <max_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <max_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <max_int_floatarr>
1c: R_ARM_CALL aux_arr_max_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <max_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <max_int_floatarr>
2c: R_ARM_CALL aux_arr_max_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_floatarr>
e: R_ARM_THM_CALL aux_arr_max_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <max_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_floatarr>
e: R_ARM_THM_CALL aux_arr_max_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <max_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <max_int_floatarr>
26: R_ARM_THM_CALL aux_arr_max_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <max_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <max_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <max_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <max_int_floatarr>
e: R_ARM_THM_CALL aux_arr_max_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <max_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <max_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_sv
28: 000080e7 jalr ra # 24 <max_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_int_floatarr+0x30>
riscv64#
0000000000000000 <max_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <max_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_int_float_sv
28: 000080e7 jalr ra # 24 <max_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_int_floatarr+0x30>
tricore#
00000000 <max_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <max_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_max_int_float_sv
24: 1d 00 00 00 j 24 <max_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_max_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <max_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <max_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <max_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <max_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_max_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
max_floatarr_intarr#
STENCIL void max_floatarr_intarr(void) {
// Element-wise max of float array and int array
aux_arr_max_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_max_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <max_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <max_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <max_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <max_floatarr_intarr+0x30>
18: ebfffffe bl 0 <max_floatarr_intarr>
18: R_ARM_CALL aux_arr_max_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <max_floatarr_intarr>
28: R_ARM_CALL aux_arr_max_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <max_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_max_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_max_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_vv
28: 000080e7 jalr ra # 24 <max_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_intarr+0x30>
riscv64#
0000000000000000 <max_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_vv
28: 000080e7 jalr ra # 24 <max_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_intarr+0x30>
tricore#
00000000 <max_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <max_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_max_float_int_vv
24: 1d 00 00 00 j 24 <max_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <max_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_max_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <max_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <max_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <max_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <max_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <max_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_max_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
max_floatarr_int#
STENCIL void max_floatarr_int(void) {
// Element-wise max of float array and int scalar
aux_arr_max_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_max_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <max_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <max_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <max_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_floatarr_int+0x34>
1c: ebfffffe bl 0 <max_floatarr_int>
1c: R_ARM_CALL aux_arr_max_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <max_floatarr_int>
2c: R_ARM_CALL aux_arr_max_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <max_floatarr_int+0x28>)
e: f7ff fffe bl 0 <max_floatarr_int>
e: R_ARM_THM_CALL aux_arr_max_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <max_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <max_floatarr_int>
e: R_ARM_THM_CALL aux_arr_max_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <max_floatarr_int>
26: R_ARM_THM_CALL aux_arr_max_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <max_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <max_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <max_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <max_floatarr_int+0x28>)
e: f7ff fffe bl 0 <max_floatarr_int>
e: R_ARM_THM_CALL aux_arr_max_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <max_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_vs
28: 000080e7 jalr ra # 24 <max_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_int+0x30>
riscv64#
0000000000000000 <max_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <max_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_vs
28: 000080e7 jalr ra # 24 <max_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_int+0x30>
tricore#
00000000 <max_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_max_float_int_vs
24: 1d 00 00 00 j 24 <max_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_max_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <max_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <max_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <max_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <max_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_max_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
max_float_intarr#
STENCIL void max_float_intarr(void) {
// Element-wise max of float scalar and int array
aux_arr_max_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <max_float_intarr>
28: R_AARCH64_CALL26 aux_arr_max_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_float_intarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <max_float_intarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <max_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <max_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_float_intarr+0x34>
1c: ebfffffe bl 0 <max_float_intarr>
1c: R_ARM_CALL aux_arr_max_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <max_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <max_float_intarr>
2c: R_ARM_CALL aux_arr_max_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_float_intarr+0x28>)
10: f7ff fffe bl 0 <max_float_intarr>
10: R_ARM_THM_CALL aux_arr_max_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <max_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <max_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <max_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <max_float_intarr>
10: R_ARM_THM_CALL aux_arr_max_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <max_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <max_float_intarr>
28: R_ARM_THM_CALL aux_arr_max_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_float_intarr+0x28>)
10: f7ff fffe bl 0 <max_float_intarr>
10: R_ARM_THM_CALL aux_arr_max_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <max_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <max_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <max_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_sv
28: 000080e7 jalr ra # 24 <max_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_float_intarr+0x30>
riscv64#
0000000000000000 <max_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <max_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <max_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_int_sv
28: 000080e7 jalr ra # 24 <max_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_float_intarr+0x30>
tricore#
00000000 <max_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <max_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <max_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <max_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <max_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_max_float_int_sv
26: 1d 00 00 00 j 26 <max_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_max_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <max_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <max_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <max_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <max_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_max_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
max_floatarr_floatarr#
STENCIL void max_floatarr_floatarr(void) {
// Element-wise max of float array and float array
aux_arr_max_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_max_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <max_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <max_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <max_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <max_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <max_floatarr_floatarr>
18: R_ARM_CALL aux_arr_max_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <max_floatarr_floatarr>
28: R_ARM_CALL aux_arr_max_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <max_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_max_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <max_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <max_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <max_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <max_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <max_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_max_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <max_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_vv
28: 000080e7 jalr ra # 24 <max_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <max_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <max_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_vv
28: 000080e7 jalr ra # 24 <max_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_floatarr+0x30>
tricore#
00000000 <max_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <max_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <max_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <max_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <max_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <max_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_max_float_float_vv
24: 1d 00 00 00 j 24 <max_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <max_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_max_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <max_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <max_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <max_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <max_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <max_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_max_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
max_floatarr_float#
STENCIL void max_floatarr_float(void) {
// Element-wise max of float array and float scalar
aux_arr_max_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <max_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_max_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_floatarr_float>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <max_floatarr_float+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <max_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <max_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_floatarr_float+0x34>
1c: ebfffffe bl 0 <max_floatarr_float>
1c: R_ARM_CALL aux_arr_max_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <max_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <max_floatarr_float>
2c: R_ARM_CALL aux_arr_max_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_floatarr_float+0x28>)
10: f7ff fffe bl 0 <max_floatarr_float>
10: R_ARM_THM_CALL aux_arr_max_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <max_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <max_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <max_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <max_floatarr_float>
10: R_ARM_THM_CALL aux_arr_max_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <max_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <max_floatarr_float>
28: R_ARM_THM_CALL aux_arr_max_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_floatarr_float+0x28>)
10: f7ff fffe bl 0 <max_floatarr_float>
10: R_ARM_THM_CALL aux_arr_max_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <max_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <max_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <max_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_vs
28: 000080e7 jalr ra # 24 <max_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_float+0x30>
riscv64#
0000000000000000 <max_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <max_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <max_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_vs
28: 000080e7 jalr ra # 24 <max_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_floatarr_float+0x30>
tricore#
00000000 <max_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <max_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <max_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <max_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <max_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_max_float_float_vs
26: 1d 00 00 00 j 26 <max_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_max_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <max_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <max_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <max_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <max_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_max_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
max_float_floatarr#
STENCIL void max_float_floatarr(void) {
// Element-wise max of float scalar and float array
aux_arr_max_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <max_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <max_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_max_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <max_float_floatarr>:
0: e59f2020 ldr r2, [pc, #32] @ 28 <max_float_floatarr+0x28>
4: e59f3020 ldr r3, [pc, #32] @ 2c <max_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <max_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <max_float_floatarr+0x34>
1c: ebfffffe bl 0 <max_float_floatarr>
1c: R_ARM_CALL aux_arr_max_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <max_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <max_float_floatarr>
2c: R_ARM_CALL aux_arr_max_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <max_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_float_floatarr+0x28>)
10: f7ff fffe bl 0 <max_float_floatarr>
10: R_ARM_THM_CALL aux_arr_max_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <max_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <max_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <max_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <max_float_floatarr>
10: R_ARM_THM_CALL aux_arr_max_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <max_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <max_float_floatarr>
28: R_ARM_THM_CALL aux_arr_max_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <max_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <max_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <max_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <max_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <max_float_floatarr+0x28>)
10: f7ff fffe bl 0 <max_float_floatarr>
10: R_ARM_THM_CALL aux_arr_max_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <max_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <max_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <max_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_sv
28: 000080e7 jalr ra # 24 <max_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_float_floatarr+0x30>
riscv64#
0000000000000000 <max_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <max_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <max_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_max_float_float_sv
28: 000080e7 jalr ra # 24 <max_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <max_float_floatarr+0x30>
tricore#
00000000 <max_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <max_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <max_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <max_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <max_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <max_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_max_float_float_sv
26: 1d 00 00 00 j 26 <max_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <max_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <max_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_max_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <max_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <max_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <max_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <max_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <max_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <max_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <max_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_max_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
gt_intarr_intarr#
STENCIL void gt_intarr_intarr(void) {
// Element-wise gt of int array and int array
aux_arr_gt_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_gt_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <gt_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <gt_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <gt_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <gt_intarr_intarr+0x30>
18: ebfffffe bl 0 <gt_intarr_intarr>
18: R_ARM_CALL aux_arr_gt_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <gt_intarr_intarr>
28: R_ARM_CALL aux_arr_gt_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <gt_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_gt_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_vv
28: 000080e7 jalr ra # 24 <gt_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_intarr+0x30>
riscv64#
0000000000000000 <gt_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_vv
28: 000080e7 jalr ra # 24 <gt_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_intarr+0x30>
tricore#
00000000 <gt_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <gt_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_int_int_vv
24: 1d 00 00 00 j 24 <gt_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <gt_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_gt_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <gt_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <gt_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <gt_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <gt_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <gt_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_gt_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
gt_intarr_int#
STENCIL void gt_intarr_int(void) {
// Element-wise gt of int array and int scalar
aux_arr_gt_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_intarr_int>
28: R_AARCH64_CALL26 aux_arr_gt_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <gt_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <gt_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_intarr_int+0x34>
1c: ebfffffe bl 0 <gt_intarr_int>
1c: R_ARM_CALL aux_arr_gt_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <gt_intarr_int>
2c: R_ARM_CALL aux_arr_gt_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_intarr_int+0x28>)
e: f7ff fffe bl 0 <gt_intarr_int>
e: R_ARM_THM_CALL aux_arr_gt_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <gt_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <gt_intarr_int>
e: R_ARM_THM_CALL aux_arr_gt_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <gt_intarr_int>
26: R_ARM_THM_CALL aux_arr_gt_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <gt_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_intarr_int+0x28>)
e: f7ff fffe bl 0 <gt_intarr_int>
e: R_ARM_THM_CALL aux_arr_gt_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <gt_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_vs
28: 000080e7 jalr ra # 24 <gt_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_int+0x30>
riscv64#
0000000000000000 <gt_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <gt_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_vs
28: 000080e7 jalr ra # 24 <gt_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_int+0x30>
tricore#
00000000 <gt_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_gt_int_int_vs
24: 1d 00 00 00 j 24 <gt_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_gt_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <gt_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <gt_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <gt_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <gt_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_gt_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
gt_int_intarr#
STENCIL void gt_int_intarr(void) {
// Element-wise gt of int scalar and int array
aux_arr_gt_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <gt_int_intarr>
28: R_AARCH64_CALL26 aux_arr_gt_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <gt_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <gt_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <gt_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <gt_int_intarr>
1c: R_ARM_CALL aux_arr_gt_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <gt_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <gt_int_intarr>
2c: R_ARM_CALL aux_arr_gt_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_intarr>
e: R_ARM_THM_CALL aux_arr_gt_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <gt_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_intarr>
e: R_ARM_THM_CALL aux_arr_gt_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <gt_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <gt_int_intarr>
26: R_ARM_THM_CALL aux_arr_gt_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <gt_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_intarr>
e: R_ARM_THM_CALL aux_arr_gt_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <gt_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <gt_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_sv
28: 000080e7 jalr ra # 24 <gt_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_int_intarr+0x30>
riscv64#
0000000000000000 <gt_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <gt_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_int_sv
28: 000080e7 jalr ra # 24 <gt_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_int_intarr+0x30>
tricore#
00000000 <gt_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <gt_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_int_int_sv
24: 1d 00 00 00 j 24 <gt_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_gt_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <gt_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <gt_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <gt_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <gt_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_gt_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
gt_intarr_floatarr#
STENCIL void gt_intarr_floatarr(void) {
// Element-wise gt of int array and float array
aux_arr_gt_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_gt_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <gt_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <gt_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <gt_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <gt_intarr_floatarr+0x30>
18: ebfffffe bl 0 <gt_intarr_floatarr>
18: R_ARM_CALL aux_arr_gt_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <gt_intarr_floatarr>
28: R_ARM_CALL aux_arr_gt_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <gt_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_gt_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_vv
28: 000080e7 jalr ra # 24 <gt_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_floatarr+0x30>
riscv64#
0000000000000000 <gt_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_vv
28: 000080e7 jalr ra # 24 <gt_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_floatarr+0x30>
tricore#
00000000 <gt_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <gt_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_int_float_vv
24: 1d 00 00 00 j 24 <gt_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <gt_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_gt_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <gt_intarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <gt_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <gt_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <gt_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <gt_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_gt_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
gt_intarr_float#
STENCIL void gt_intarr_float(void) {
// Element-wise gt of int array and float scalar
aux_arr_gt_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_intarr_float>
28: R_AARCH64_CALL26 aux_arr_gt_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <gt_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <gt_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_intarr_float+0x34>
1c: ebfffffe bl 0 <gt_intarr_float>
1c: R_ARM_CALL aux_arr_gt_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <gt_intarr_float>
2c: R_ARM_CALL aux_arr_gt_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_intarr_float+0x28>)
10: f7ff fffe bl 0 <gt_intarr_float>
10: R_ARM_THM_CALL aux_arr_gt_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <gt_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <gt_intarr_float>
10: R_ARM_THM_CALL aux_arr_gt_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <gt_intarr_float>
28: R_ARM_THM_CALL aux_arr_gt_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_intarr_float+0x28>)
10: f7ff fffe bl 0 <gt_intarr_float>
10: R_ARM_THM_CALL aux_arr_gt_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <gt_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <gt_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_vs
28: 000080e7 jalr ra # 24 <gt_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_float+0x30>
riscv64#
0000000000000000 <gt_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <gt_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <gt_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_vs
28: 000080e7 jalr ra # 24 <gt_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_intarr_float+0x30>
tricore#
00000000 <gt_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <gt_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <gt_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_gt_int_float_vs
26: 1d 00 00 00 j 26 <gt_intarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_gt_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_intarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <gt_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <gt_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <gt_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <gt_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_gt_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
gt_int_floatarr#
STENCIL void gt_int_floatarr(void) {
// Element-wise gt of int scalar and float array
aux_arr_gt_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <gt_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_gt_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <gt_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <gt_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <gt_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <gt_int_floatarr>
1c: R_ARM_CALL aux_arr_gt_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <gt_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <gt_int_floatarr>
2c: R_ARM_CALL aux_arr_gt_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_floatarr>
e: R_ARM_THM_CALL aux_arr_gt_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <gt_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_floatarr>
e: R_ARM_THM_CALL aux_arr_gt_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <gt_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <gt_int_floatarr>
26: R_ARM_THM_CALL aux_arr_gt_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <gt_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <gt_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <gt_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <gt_int_floatarr>
e: R_ARM_THM_CALL aux_arr_gt_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <gt_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <gt_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_sv
28: 000080e7 jalr ra # 24 <gt_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_int_floatarr+0x30>
riscv64#
0000000000000000 <gt_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <gt_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_int_float_sv
28: 000080e7 jalr ra # 24 <gt_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_int_floatarr+0x30>
tricore#
00000000 <gt_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <gt_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_int_float_sv
24: 1d 00 00 00 j 24 <gt_int_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_gt_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_int_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <gt_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <gt_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <gt_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <gt_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_gt_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
gt_floatarr_intarr#
STENCIL void gt_floatarr_intarr(void) {
// Element-wise gt of float array and int array
aux_arr_gt_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_gt_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <gt_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <gt_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <gt_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <gt_floatarr_intarr+0x30>
18: ebfffffe bl 0 <gt_floatarr_intarr>
18: R_ARM_CALL aux_arr_gt_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <gt_floatarr_intarr>
28: R_ARM_CALL aux_arr_gt_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <gt_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_gt_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_gt_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_vv
28: 000080e7 jalr ra # 24 <gt_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_intarr+0x30>
riscv64#
0000000000000000 <gt_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_vv
28: 000080e7 jalr ra # 24 <gt_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_intarr+0x30>
tricore#
00000000 <gt_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <gt_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_float_int_vv
24: 1d 00 00 00 j 24 <gt_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <gt_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_gt_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <gt_floatarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <gt_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <gt_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <gt_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <gt_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_gt_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
gt_floatarr_int#
STENCIL void gt_floatarr_int(void) {
// Element-wise gt of float array and int scalar
aux_arr_gt_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_gt_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <gt_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <gt_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_floatarr_int+0x34>
1c: ebfffffe bl 0 <gt_floatarr_int>
1c: R_ARM_CALL aux_arr_gt_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <gt_floatarr_int>
2c: R_ARM_CALL aux_arr_gt_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_floatarr_int+0x28>)
e: f7ff fffe bl 0 <gt_floatarr_int>
e: R_ARM_THM_CALL aux_arr_gt_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <gt_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <gt_floatarr_int>
e: R_ARM_THM_CALL aux_arr_gt_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <gt_floatarr_int>
26: R_ARM_THM_CALL aux_arr_gt_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <gt_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <gt_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <gt_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_floatarr_int+0x28>)
e: f7ff fffe bl 0 <gt_floatarr_int>
e: R_ARM_THM_CALL aux_arr_gt_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <gt_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_vs
28: 000080e7 jalr ra # 24 <gt_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_int+0x30>
riscv64#
0000000000000000 <gt_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <gt_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_vs
28: 000080e7 jalr ra # 24 <gt_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_int+0x30>
tricore#
00000000 <gt_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_gt_float_int_vs
24: 1d 00 00 00 j 24 <gt_floatarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_gt_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_floatarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <gt_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <gt_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <gt_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <gt_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_gt_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
gt_float_intarr#
STENCIL void gt_float_intarr(void) {
// Element-wise gt of float scalar and int array
aux_arr_gt_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <gt_float_intarr>
28: R_AARCH64_CALL26 aux_arr_gt_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <gt_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <gt_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_float_intarr+0x34>
1c: ebfffffe bl 0 <gt_float_intarr>
1c: R_ARM_CALL aux_arr_gt_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <gt_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <gt_float_intarr>
2c: R_ARM_CALL aux_arr_gt_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_float_intarr+0x28>)
10: f7ff fffe bl 0 <gt_float_intarr>
10: R_ARM_THM_CALL aux_arr_gt_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <gt_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <gt_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <gt_float_intarr>
10: R_ARM_THM_CALL aux_arr_gt_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <gt_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <gt_float_intarr>
28: R_ARM_THM_CALL aux_arr_gt_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_float_intarr+0x28>)
10: f7ff fffe bl 0 <gt_float_intarr>
10: R_ARM_THM_CALL aux_arr_gt_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <gt_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <gt_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <gt_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_sv
28: 000080e7 jalr ra # 24 <gt_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_float_intarr+0x30>
riscv64#
0000000000000000 <gt_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <gt_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <gt_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_int_sv
28: 000080e7 jalr ra # 24 <gt_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_float_intarr+0x30>
tricore#
00000000 <gt_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <gt_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <gt_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_gt_float_int_sv
26: 1d 00 00 00 j 26 <gt_float_intarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_gt_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_float_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <gt_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <gt_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <gt_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <gt_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_gt_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
gt_floatarr_floatarr#
STENCIL void gt_floatarr_floatarr(void) {
// Element-wise gt of float array and float array
aux_arr_gt_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_gt_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <gt_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <gt_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <gt_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <gt_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <gt_floatarr_floatarr>
18: R_ARM_CALL aux_arr_gt_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <gt_floatarr_floatarr>
28: R_ARM_CALL aux_arr_gt_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <gt_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_gt_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <gt_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <gt_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <gt_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <gt_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <gt_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_gt_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <gt_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_vv
28: 000080e7 jalr ra # 24 <gt_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <gt_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <gt_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_vv
28: 000080e7 jalr ra # 24 <gt_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_floatarr+0x30>
tricore#
00000000 <gt_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <gt_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <gt_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <gt_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_gt_float_float_vv
24: 1d 00 00 00 j 24 <gt_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <gt_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_gt_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <gt_floatarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <gt_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <gt_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <gt_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <gt_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_gt_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
gt_floatarr_float#
STENCIL void gt_floatarr_float(void) {
// Element-wise gt of float array and float scalar
aux_arr_gt_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <gt_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_gt_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <gt_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <gt_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_floatarr_float+0x34>
1c: ebfffffe bl 0 <gt_floatarr_float>
1c: R_ARM_CALL aux_arr_gt_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <gt_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <gt_floatarr_float>
2c: R_ARM_CALL aux_arr_gt_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_floatarr_float+0x28>)
10: f7ff fffe bl 0 <gt_floatarr_float>
10: R_ARM_THM_CALL aux_arr_gt_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <gt_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <gt_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <gt_floatarr_float>
10: R_ARM_THM_CALL aux_arr_gt_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <gt_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <gt_floatarr_float>
28: R_ARM_THM_CALL aux_arr_gt_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_floatarr_float+0x28>)
10: f7ff fffe bl 0 <gt_floatarr_float>
10: R_ARM_THM_CALL aux_arr_gt_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <gt_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <gt_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <gt_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_vs
28: 000080e7 jalr ra # 24 <gt_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_float+0x30>
riscv64#
0000000000000000 <gt_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <gt_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <gt_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_vs
28: 000080e7 jalr ra # 24 <gt_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_floatarr_float+0x30>
tricore#
00000000 <gt_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <gt_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <gt_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_gt_float_float_vs
26: 1d 00 00 00 j 26 <gt_floatarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_gt_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_floatarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <gt_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <gt_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <gt_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <gt_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_gt_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
gt_float_floatarr#
STENCIL void gt_float_floatarr(void) {
// Element-wise gt of float scalar and float array
aux_arr_gt_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <gt_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <gt_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_gt_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <gt_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <gt_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <gt_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <gt_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <gt_float_floatarr+0x34>
1c: ebfffffe bl 0 <gt_float_floatarr>
1c: R_ARM_CALL aux_arr_gt_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <gt_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <gt_float_floatarr>
2c: R_ARM_CALL aux_arr_gt_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <gt_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_float_floatarr+0x28>)
10: f7ff fffe bl 0 <gt_float_floatarr>
10: R_ARM_THM_CALL aux_arr_gt_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <gt_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <gt_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <gt_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <gt_float_floatarr>
10: R_ARM_THM_CALL aux_arr_gt_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <gt_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <gt_float_floatarr>
28: R_ARM_THM_CALL aux_arr_gt_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <gt_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <gt_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <gt_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <gt_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <gt_float_floatarr+0x28>)
10: f7ff fffe bl 0 <gt_float_floatarr>
10: R_ARM_THM_CALL aux_arr_gt_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <gt_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <gt_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <gt_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_sv
28: 000080e7 jalr ra # 24 <gt_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_float_floatarr+0x30>
riscv64#
0000000000000000 <gt_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <gt_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <gt_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_gt_float_float_sv
28: 000080e7 jalr ra # 24 <gt_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <gt_float_floatarr+0x30>
tricore#
00000000 <gt_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <gt_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <gt_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <gt_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <gt_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <gt_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_gt_float_float_sv
26: 1d 00 00 00 j 26 <gt_float_floatarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <gt_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <gt_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_gt_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <gt_float_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <gt_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <gt_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <gt_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <gt_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <gt_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <gt_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_gt_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ge_intarr_intarr#
STENCIL void ge_intarr_intarr(void) {
// Element-wise ge of int array and int array
aux_arr_ge_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_ge_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ge_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ge_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ge_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ge_intarr_intarr+0x30>
18: ebfffffe bl 0 <ge_intarr_intarr>
18: R_ARM_CALL aux_arr_ge_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ge_intarr_intarr>
28: R_ARM_CALL aux_arr_ge_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ge_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_ge_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_vv
28: 000080e7 jalr ra # 24 <ge_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_intarr+0x30>
riscv64#
0000000000000000 <ge_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_vv
28: 000080e7 jalr ra # 24 <ge_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_intarr+0x30>
tricore#
00000000 <ge_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ge_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_int_int_vv
24: 1d 00 00 00 j 24 <ge_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ge_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_ge_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ge_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ge_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ge_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ge_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ge_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_ge_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ge_intarr_int#
STENCIL void ge_intarr_int(void) {
// Element-wise ge of int array and int scalar
aux_arr_ge_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_intarr_int>
28: R_AARCH64_CALL26 aux_arr_ge_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <ge_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ge_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_intarr_int+0x34>
1c: ebfffffe bl 0 <ge_intarr_int>
1c: R_ARM_CALL aux_arr_ge_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <ge_intarr_int>
2c: R_ARM_CALL aux_arr_ge_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_intarr_int+0x28>)
e: f7ff fffe bl 0 <ge_intarr_int>
e: R_ARM_THM_CALL aux_arr_ge_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <ge_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <ge_intarr_int>
e: R_ARM_THM_CALL aux_arr_ge_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ge_intarr_int>
26: R_ARM_THM_CALL aux_arr_ge_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ge_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_intarr_int+0x28>)
e: f7ff fffe bl 0 <ge_intarr_int>
e: R_ARM_THM_CALL aux_arr_ge_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <ge_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_vs
28: 000080e7 jalr ra # 24 <ge_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_int+0x30>
riscv64#
0000000000000000 <ge_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <ge_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_vs
28: 000080e7 jalr ra # 24 <ge_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_int+0x30>
tricore#
00000000 <ge_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_ge_int_int_vs
24: 1d 00 00 00 j 24 <ge_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_ge_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ge_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ge_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <ge_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <ge_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_ge_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ge_int_intarr#
STENCIL void ge_int_intarr(void) {
// Element-wise ge of int scalar and int array
aux_arr_ge_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ge_int_intarr>
28: R_AARCH64_CALL26 aux_arr_ge_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <ge_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ge_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <ge_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <ge_int_intarr>
1c: R_ARM_CALL aux_arr_ge_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ge_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <ge_int_intarr>
2c: R_ARM_CALL aux_arr_ge_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_intarr>
e: R_ARM_THM_CALL aux_arr_ge_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ge_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_intarr>
e: R_ARM_THM_CALL aux_arr_ge_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ge_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ge_int_intarr>
26: R_ARM_THM_CALL aux_arr_ge_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ge_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_intarr>
e: R_ARM_THM_CALL aux_arr_ge_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ge_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <ge_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_sv
28: 000080e7 jalr ra # 24 <ge_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_int_intarr+0x30>
riscv64#
0000000000000000 <ge_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <ge_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_int_sv
28: 000080e7 jalr ra # 24 <ge_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_int_intarr+0x30>
tricore#
00000000 <ge_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <ge_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_int_int_sv
24: 1d 00 00 00 j 24 <ge_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_ge_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ge_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ge_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <ge_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <ge_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_ge_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ge_intarr_floatarr#
STENCIL void ge_intarr_floatarr(void) {
// Element-wise ge of int array and float array
aux_arr_ge_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_ge_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ge_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ge_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ge_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ge_intarr_floatarr+0x30>
18: ebfffffe bl 0 <ge_intarr_floatarr>
18: R_ARM_CALL aux_arr_ge_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ge_intarr_floatarr>
28: R_ARM_CALL aux_arr_ge_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ge_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_ge_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_vv
28: 000080e7 jalr ra # 24 <ge_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_floatarr+0x30>
riscv64#
0000000000000000 <ge_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_vv
28: 000080e7 jalr ra # 24 <ge_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_floatarr+0x30>
tricore#
00000000 <ge_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ge_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_int_float_vv
24: 1d 00 00 00 j 24 <ge_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ge_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_ge_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ge_intarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ge_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ge_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ge_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ge_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_ge_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ge_intarr_float#
STENCIL void ge_intarr_float(void) {
// Element-wise ge of int array and float scalar
aux_arr_ge_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_intarr_float>
28: R_AARCH64_CALL26 aux_arr_ge_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ge_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ge_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_intarr_float+0x34>
1c: ebfffffe bl 0 <ge_intarr_float>
1c: R_ARM_CALL aux_arr_ge_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ge_intarr_float>
2c: R_ARM_CALL aux_arr_ge_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_intarr_float+0x28>)
10: f7ff fffe bl 0 <ge_intarr_float>
10: R_ARM_THM_CALL aux_arr_ge_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ge_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ge_intarr_float>
10: R_ARM_THM_CALL aux_arr_ge_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ge_intarr_float>
28: R_ARM_THM_CALL aux_arr_ge_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_intarr_float+0x28>)
10: f7ff fffe bl 0 <ge_intarr_float>
10: R_ARM_THM_CALL aux_arr_ge_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ge_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <ge_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_vs
28: 000080e7 jalr ra # 24 <ge_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_float+0x30>
riscv64#
0000000000000000 <ge_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ge_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <ge_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_vs
28: 000080e7 jalr ra # 24 <ge_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_intarr_float+0x30>
tricore#
00000000 <ge_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ge_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <ge_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_ge_int_float_vs
26: 1d 00 00 00 j 26 <ge_intarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_ge_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_intarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ge_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ge_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ge_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <ge_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_ge_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ge_int_floatarr#
STENCIL void ge_int_floatarr(void) {
// Element-wise ge of int scalar and float array
aux_arr_ge_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ge_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_ge_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <ge_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ge_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <ge_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <ge_int_floatarr>
1c: R_ARM_CALL aux_arr_ge_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ge_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <ge_int_floatarr>
2c: R_ARM_CALL aux_arr_ge_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ge_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ge_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ge_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ge_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ge_int_floatarr>
26: R_ARM_THM_CALL aux_arr_ge_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ge_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ge_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ge_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ge_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ge_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ge_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <ge_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_sv
28: 000080e7 jalr ra # 24 <ge_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_int_floatarr+0x30>
riscv64#
0000000000000000 <ge_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <ge_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_int_float_sv
28: 000080e7 jalr ra # 24 <ge_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_int_floatarr+0x30>
tricore#
00000000 <ge_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <ge_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_int_float_sv
24: 1d 00 00 00 j 24 <ge_int_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_ge_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_int_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ge_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ge_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <ge_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <ge_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_ge_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ge_floatarr_intarr#
STENCIL void ge_floatarr_intarr(void) {
// Element-wise ge of float array and int array
aux_arr_ge_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_ge_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ge_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ge_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ge_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ge_floatarr_intarr+0x30>
18: ebfffffe bl 0 <ge_floatarr_intarr>
18: R_ARM_CALL aux_arr_ge_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ge_floatarr_intarr>
28: R_ARM_CALL aux_arr_ge_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ge_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_ge_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ge_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_vv
28: 000080e7 jalr ra # 24 <ge_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_intarr+0x30>
riscv64#
0000000000000000 <ge_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_vv
28: 000080e7 jalr ra # 24 <ge_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_intarr+0x30>
tricore#
00000000 <ge_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ge_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_float_int_vv
24: 1d 00 00 00 j 24 <ge_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ge_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_ge_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ge_floatarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ge_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ge_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ge_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ge_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_ge_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ge_floatarr_int#
STENCIL void ge_floatarr_int(void) {
// Element-wise ge of float array and int scalar
aux_arr_ge_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_ge_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <ge_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ge_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_floatarr_int+0x34>
1c: ebfffffe bl 0 <ge_floatarr_int>
1c: R_ARM_CALL aux_arr_ge_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <ge_floatarr_int>
2c: R_ARM_CALL aux_arr_ge_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_floatarr_int+0x28>)
e: f7ff fffe bl 0 <ge_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ge_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <ge_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <ge_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ge_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ge_floatarr_int>
26: R_ARM_THM_CALL aux_arr_ge_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ge_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ge_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ge_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_floatarr_int+0x28>)
e: f7ff fffe bl 0 <ge_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ge_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <ge_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_vs
28: 000080e7 jalr ra # 24 <ge_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_int+0x30>
riscv64#
0000000000000000 <ge_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <ge_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_vs
28: 000080e7 jalr ra # 24 <ge_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_int+0x30>
tricore#
00000000 <ge_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_ge_float_int_vs
24: 1d 00 00 00 j 24 <ge_floatarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_ge_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_floatarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ge_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ge_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <ge_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <ge_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_ge_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ge_float_intarr#
STENCIL void ge_float_intarr(void) {
// Element-wise ge of float scalar and int array
aux_arr_ge_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ge_float_intarr>
28: R_AARCH64_CALL26 aux_arr_ge_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ge_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ge_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_float_intarr+0x34>
1c: ebfffffe bl 0 <ge_float_intarr>
1c: R_ARM_CALL aux_arr_ge_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ge_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ge_float_intarr>
2c: R_ARM_CALL aux_arr_ge_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_float_intarr+0x28>)
10: f7ff fffe bl 0 <ge_float_intarr>
10: R_ARM_THM_CALL aux_arr_ge_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ge_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ge_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ge_float_intarr>
10: R_ARM_THM_CALL aux_arr_ge_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ge_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ge_float_intarr>
28: R_ARM_THM_CALL aux_arr_ge_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_float_intarr+0x28>)
10: f7ff fffe bl 0 <ge_float_intarr>
10: R_ARM_THM_CALL aux_arr_ge_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ge_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ge_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <ge_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_sv
28: 000080e7 jalr ra # 24 <ge_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_float_intarr+0x30>
riscv64#
0000000000000000 <ge_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ge_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <ge_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_int_sv
28: 000080e7 jalr ra # 24 <ge_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_float_intarr+0x30>
tricore#
00000000 <ge_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ge_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <ge_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_ge_float_int_sv
26: 1d 00 00 00 j 26 <ge_float_intarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_ge_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_float_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ge_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ge_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ge_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <ge_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_ge_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ge_floatarr_floatarr#
STENCIL void ge_floatarr_floatarr(void) {
// Element-wise ge of float array and float array
aux_arr_ge_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_ge_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ge_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ge_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ge_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ge_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <ge_floatarr_floatarr>
18: R_ARM_CALL aux_arr_ge_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ge_floatarr_floatarr>
28: R_ARM_CALL aux_arr_ge_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ge_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_ge_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ge_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ge_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ge_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ge_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ge_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ge_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ge_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_vv
28: 000080e7 jalr ra # 24 <ge_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <ge_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ge_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_vv
28: 000080e7 jalr ra # 24 <ge_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_floatarr+0x30>
tricore#
00000000 <ge_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ge_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ge_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ge_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ge_float_float_vv
24: 1d 00 00 00 j 24 <ge_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ge_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_ge_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ge_floatarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ge_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ge_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ge_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ge_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_ge_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ge_floatarr_float#
STENCIL void ge_floatarr_float(void) {
// Element-wise ge of float array and float scalar
aux_arr_ge_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ge_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_ge_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ge_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ge_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_floatarr_float+0x34>
1c: ebfffffe bl 0 <ge_floatarr_float>
1c: R_ARM_CALL aux_arr_ge_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ge_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ge_floatarr_float>
2c: R_ARM_CALL aux_arr_ge_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_floatarr_float+0x28>)
10: f7ff fffe bl 0 <ge_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ge_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ge_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ge_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ge_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ge_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ge_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ge_floatarr_float>
28: R_ARM_THM_CALL aux_arr_ge_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_floatarr_float+0x28>)
10: f7ff fffe bl 0 <ge_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ge_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ge_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ge_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <ge_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_vs
28: 000080e7 jalr ra # 24 <ge_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_float+0x30>
riscv64#
0000000000000000 <ge_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ge_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <ge_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_vs
28: 000080e7 jalr ra # 24 <ge_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_floatarr_float+0x30>
tricore#
00000000 <ge_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ge_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <ge_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_ge_float_float_vs
26: 1d 00 00 00 j 26 <ge_floatarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_ge_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_floatarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ge_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ge_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ge_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <ge_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_ge_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ge_float_floatarr#
STENCIL void ge_float_floatarr(void) {
// Element-wise ge of float scalar and float array
aux_arr_ge_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ge_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ge_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_ge_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ge_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ge_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ge_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ge_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ge_float_floatarr+0x34>
1c: ebfffffe bl 0 <ge_float_floatarr>
1c: R_ARM_CALL aux_arr_ge_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ge_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ge_float_floatarr>
2c: R_ARM_CALL aux_arr_ge_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ge_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_float_floatarr+0x28>)
10: f7ff fffe bl 0 <ge_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ge_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ge_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ge_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ge_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ge_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ge_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ge_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ge_float_floatarr>
28: R_ARM_THM_CALL aux_arr_ge_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ge_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ge_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ge_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ge_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ge_float_floatarr+0x28>)
10: f7ff fffe bl 0 <ge_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ge_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ge_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ge_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <ge_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_sv
28: 000080e7 jalr ra # 24 <ge_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_float_floatarr+0x30>
riscv64#
0000000000000000 <ge_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ge_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <ge_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ge_float_float_sv
28: 000080e7 jalr ra # 24 <ge_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ge_float_floatarr+0x30>
tricore#
00000000 <ge_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ge_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ge_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ge_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ge_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <ge_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_ge_float_float_sv
26: 1d 00 00 00 j 26 <ge_float_floatarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ge_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ge_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_ge_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ge_float_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ge_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ge_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ge_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ge_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ge_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <ge_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_ge_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
eq_intarr_intarr#
STENCIL void eq_intarr_intarr(void) {
// Element-wise eq of int array and int array
aux_arr_eq_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_eq_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <eq_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <eq_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <eq_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <eq_intarr_intarr+0x30>
18: ebfffffe bl 0 <eq_intarr_intarr>
18: R_ARM_CALL aux_arr_eq_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <eq_intarr_intarr>
28: R_ARM_CALL aux_arr_eq_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <eq_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_eq_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_vv
28: 000080e7 jalr ra # 24 <eq_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_intarr+0x30>
riscv64#
0000000000000000 <eq_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_vv
28: 000080e7 jalr ra # 24 <eq_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_intarr+0x30>
tricore#
00000000 <eq_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <eq_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_int_int_vv
24: 1d 00 00 00 j 24 <eq_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <eq_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_eq_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <eq_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <eq_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <eq_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <eq_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <eq_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_eq_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
eq_intarr_int#
STENCIL void eq_intarr_int(void) {
// Element-wise eq of int array and int scalar
aux_arr_eq_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_intarr_int>
28: R_AARCH64_CALL26 aux_arr_eq_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <eq_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <eq_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_intarr_int+0x34>
1c: ebfffffe bl 0 <eq_intarr_int>
1c: R_ARM_CALL aux_arr_eq_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <eq_intarr_int>
2c: R_ARM_CALL aux_arr_eq_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_intarr_int+0x28>)
e: f7ff fffe bl 0 <eq_intarr_int>
e: R_ARM_THM_CALL aux_arr_eq_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <eq_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <eq_intarr_int>
e: R_ARM_THM_CALL aux_arr_eq_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <eq_intarr_int>
26: R_ARM_THM_CALL aux_arr_eq_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <eq_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_intarr_int+0x28>)
e: f7ff fffe bl 0 <eq_intarr_int>
e: R_ARM_THM_CALL aux_arr_eq_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <eq_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_vs
28: 000080e7 jalr ra # 24 <eq_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_int+0x30>
riscv64#
0000000000000000 <eq_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <eq_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_vs
28: 000080e7 jalr ra # 24 <eq_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_int+0x30>
tricore#
00000000 <eq_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_eq_int_int_vs
24: 1d 00 00 00 j 24 <eq_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_eq_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <eq_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <eq_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <eq_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <eq_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_eq_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
eq_int_intarr#
STENCIL void eq_int_intarr(void) {
// Element-wise eq of int scalar and int array
aux_arr_eq_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <eq_int_intarr>
28: R_AARCH64_CALL26 aux_arr_eq_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <eq_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <eq_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <eq_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <eq_int_intarr>
1c: R_ARM_CALL aux_arr_eq_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <eq_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <eq_int_intarr>
2c: R_ARM_CALL aux_arr_eq_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_intarr>
e: R_ARM_THM_CALL aux_arr_eq_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <eq_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_intarr>
e: R_ARM_THM_CALL aux_arr_eq_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <eq_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <eq_int_intarr>
26: R_ARM_THM_CALL aux_arr_eq_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <eq_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_intarr>
e: R_ARM_THM_CALL aux_arr_eq_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <eq_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <eq_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_sv
28: 000080e7 jalr ra # 24 <eq_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_int_intarr+0x30>
riscv64#
0000000000000000 <eq_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <eq_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_int_sv
28: 000080e7 jalr ra # 24 <eq_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_int_intarr+0x30>
tricore#
00000000 <eq_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <eq_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_int_int_sv
24: 1d 00 00 00 j 24 <eq_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_eq_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <eq_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <eq_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <eq_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <eq_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_eq_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
eq_intarr_floatarr#
STENCIL void eq_intarr_floatarr(void) {
// Element-wise eq of int array and float array
aux_arr_eq_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_eq_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <eq_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <eq_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <eq_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <eq_intarr_floatarr+0x30>
18: ebfffffe bl 0 <eq_intarr_floatarr>
18: R_ARM_CALL aux_arr_eq_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <eq_intarr_floatarr>
28: R_ARM_CALL aux_arr_eq_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <eq_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_eq_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_vv
28: 000080e7 jalr ra # 24 <eq_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_floatarr+0x30>
riscv64#
0000000000000000 <eq_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_vv
28: 000080e7 jalr ra # 24 <eq_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_floatarr+0x30>
tricore#
00000000 <eq_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <eq_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_int_float_vv
24: 1d 00 00 00 j 24 <eq_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <eq_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_eq_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <eq_intarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <eq_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <eq_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <eq_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <eq_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_eq_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
eq_intarr_float#
STENCIL void eq_intarr_float(void) {
// Element-wise eq of int array and float scalar
aux_arr_eq_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_intarr_float>
28: R_AARCH64_CALL26 aux_arr_eq_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <eq_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <eq_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_intarr_float+0x34>
1c: ebfffffe bl 0 <eq_intarr_float>
1c: R_ARM_CALL aux_arr_eq_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <eq_intarr_float>
2c: R_ARM_CALL aux_arr_eq_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_intarr_float+0x28>)
10: f7ff fffe bl 0 <eq_intarr_float>
10: R_ARM_THM_CALL aux_arr_eq_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <eq_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <eq_intarr_float>
10: R_ARM_THM_CALL aux_arr_eq_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <eq_intarr_float>
28: R_ARM_THM_CALL aux_arr_eq_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_intarr_float+0x28>)
10: f7ff fffe bl 0 <eq_intarr_float>
10: R_ARM_THM_CALL aux_arr_eq_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <eq_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <eq_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_vs
28: 000080e7 jalr ra # 24 <eq_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_float+0x30>
riscv64#
0000000000000000 <eq_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <eq_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <eq_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_vs
28: 000080e7 jalr ra # 24 <eq_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_intarr_float+0x30>
tricore#
00000000 <eq_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <eq_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <eq_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_eq_int_float_vs
26: 1d 00 00 00 j 26 <eq_intarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_eq_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_intarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <eq_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <eq_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <eq_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <eq_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_eq_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
eq_int_floatarr#
STENCIL void eq_int_floatarr(void) {
// Element-wise eq of int scalar and float array
aux_arr_eq_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <eq_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_eq_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <eq_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <eq_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <eq_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <eq_int_floatarr>
1c: R_ARM_CALL aux_arr_eq_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <eq_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <eq_int_floatarr>
2c: R_ARM_CALL aux_arr_eq_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_floatarr>
e: R_ARM_THM_CALL aux_arr_eq_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <eq_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_floatarr>
e: R_ARM_THM_CALL aux_arr_eq_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <eq_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <eq_int_floatarr>
26: R_ARM_THM_CALL aux_arr_eq_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <eq_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <eq_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <eq_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <eq_int_floatarr>
e: R_ARM_THM_CALL aux_arr_eq_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <eq_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <eq_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_sv
28: 000080e7 jalr ra # 24 <eq_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_int_floatarr+0x30>
riscv64#
0000000000000000 <eq_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <eq_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_int_float_sv
28: 000080e7 jalr ra # 24 <eq_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_int_floatarr+0x30>
tricore#
00000000 <eq_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <eq_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_int_float_sv
24: 1d 00 00 00 j 24 <eq_int_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_eq_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_int_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <eq_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <eq_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <eq_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <eq_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_eq_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
eq_floatarr_intarr#
STENCIL void eq_floatarr_intarr(void) {
// Element-wise eq of float array and int array
aux_arr_eq_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_eq_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <eq_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <eq_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <eq_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <eq_floatarr_intarr+0x30>
18: ebfffffe bl 0 <eq_floatarr_intarr>
18: R_ARM_CALL aux_arr_eq_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <eq_floatarr_intarr>
28: R_ARM_CALL aux_arr_eq_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <eq_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_eq_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_eq_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_vv
28: 000080e7 jalr ra # 24 <eq_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_intarr+0x30>
riscv64#
0000000000000000 <eq_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_vv
28: 000080e7 jalr ra # 24 <eq_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_intarr+0x30>
tricore#
00000000 <eq_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <eq_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_float_int_vv
24: 1d 00 00 00 j 24 <eq_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <eq_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_eq_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <eq_floatarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <eq_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <eq_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <eq_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <eq_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_eq_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
eq_floatarr_int#
STENCIL void eq_floatarr_int(void) {
// Element-wise eq of float array and int scalar
aux_arr_eq_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_eq_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <eq_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <eq_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_floatarr_int+0x34>
1c: ebfffffe bl 0 <eq_floatarr_int>
1c: R_ARM_CALL aux_arr_eq_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <eq_floatarr_int>
2c: R_ARM_CALL aux_arr_eq_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_floatarr_int+0x28>)
e: f7ff fffe bl 0 <eq_floatarr_int>
e: R_ARM_THM_CALL aux_arr_eq_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <eq_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <eq_floatarr_int>
e: R_ARM_THM_CALL aux_arr_eq_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <eq_floatarr_int>
26: R_ARM_THM_CALL aux_arr_eq_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <eq_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <eq_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <eq_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_floatarr_int+0x28>)
e: f7ff fffe bl 0 <eq_floatarr_int>
e: R_ARM_THM_CALL aux_arr_eq_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <eq_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_vs
28: 000080e7 jalr ra # 24 <eq_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_int+0x30>
riscv64#
0000000000000000 <eq_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <eq_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_vs
28: 000080e7 jalr ra # 24 <eq_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_int+0x30>
tricore#
00000000 <eq_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_eq_float_int_vs
24: 1d 00 00 00 j 24 <eq_floatarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_eq_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_floatarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <eq_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <eq_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <eq_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <eq_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_eq_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
eq_float_intarr#
STENCIL void eq_float_intarr(void) {
// Element-wise eq of float scalar and int array
aux_arr_eq_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <eq_float_intarr>
28: R_AARCH64_CALL26 aux_arr_eq_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <eq_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <eq_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_float_intarr+0x34>
1c: ebfffffe bl 0 <eq_float_intarr>
1c: R_ARM_CALL aux_arr_eq_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <eq_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <eq_float_intarr>
2c: R_ARM_CALL aux_arr_eq_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_float_intarr+0x28>)
10: f7ff fffe bl 0 <eq_float_intarr>
10: R_ARM_THM_CALL aux_arr_eq_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <eq_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <eq_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <eq_float_intarr>
10: R_ARM_THM_CALL aux_arr_eq_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <eq_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <eq_float_intarr>
28: R_ARM_THM_CALL aux_arr_eq_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_float_intarr+0x28>)
10: f7ff fffe bl 0 <eq_float_intarr>
10: R_ARM_THM_CALL aux_arr_eq_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <eq_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <eq_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <eq_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_sv
28: 000080e7 jalr ra # 24 <eq_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_float_intarr+0x30>
riscv64#
0000000000000000 <eq_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <eq_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <eq_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_int_sv
28: 000080e7 jalr ra # 24 <eq_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_float_intarr+0x30>
tricore#
00000000 <eq_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <eq_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <eq_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_eq_float_int_sv
26: 1d 00 00 00 j 26 <eq_float_intarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_eq_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_float_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <eq_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <eq_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <eq_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <eq_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_eq_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
eq_floatarr_floatarr#
STENCIL void eq_floatarr_floatarr(void) {
// Element-wise eq of float array and float array
aux_arr_eq_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_eq_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <eq_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <eq_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <eq_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <eq_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <eq_floatarr_floatarr>
18: R_ARM_CALL aux_arr_eq_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <eq_floatarr_floatarr>
28: R_ARM_CALL aux_arr_eq_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <eq_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_eq_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <eq_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <eq_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <eq_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <eq_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <eq_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_eq_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <eq_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_vv
28: 000080e7 jalr ra # 24 <eq_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <eq_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <eq_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_vv
28: 000080e7 jalr ra # 24 <eq_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_floatarr+0x30>
tricore#
00000000 <eq_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <eq_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <eq_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <eq_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_eq_float_float_vv
24: 1d 00 00 00 j 24 <eq_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <eq_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_eq_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <eq_floatarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <eq_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <eq_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <eq_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <eq_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_eq_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
eq_floatarr_float#
STENCIL void eq_floatarr_float(void) {
// Element-wise eq of float array and float scalar
aux_arr_eq_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <eq_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_eq_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <eq_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <eq_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_floatarr_float+0x34>
1c: ebfffffe bl 0 <eq_floatarr_float>
1c: R_ARM_CALL aux_arr_eq_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <eq_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <eq_floatarr_float>
2c: R_ARM_CALL aux_arr_eq_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_floatarr_float+0x28>)
10: f7ff fffe bl 0 <eq_floatarr_float>
10: R_ARM_THM_CALL aux_arr_eq_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <eq_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <eq_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <eq_floatarr_float>
10: R_ARM_THM_CALL aux_arr_eq_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <eq_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <eq_floatarr_float>
28: R_ARM_THM_CALL aux_arr_eq_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_floatarr_float+0x28>)
10: f7ff fffe bl 0 <eq_floatarr_float>
10: R_ARM_THM_CALL aux_arr_eq_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <eq_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <eq_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <eq_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_vs
28: 000080e7 jalr ra # 24 <eq_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_float+0x30>
riscv64#
0000000000000000 <eq_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <eq_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <eq_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_vs
28: 000080e7 jalr ra # 24 <eq_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_floatarr_float+0x30>
tricore#
00000000 <eq_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <eq_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <eq_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_eq_float_float_vs
26: 1d 00 00 00 j 26 <eq_floatarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_eq_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_floatarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <eq_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <eq_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <eq_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <eq_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_eq_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
eq_float_floatarr#
STENCIL void eq_float_floatarr(void) {
// Element-wise eq of float scalar and float array
aux_arr_eq_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <eq_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <eq_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_eq_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <eq_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <eq_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <eq_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <eq_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <eq_float_floatarr+0x34>
1c: ebfffffe bl 0 <eq_float_floatarr>
1c: R_ARM_CALL aux_arr_eq_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <eq_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <eq_float_floatarr>
2c: R_ARM_CALL aux_arr_eq_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <eq_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_float_floatarr+0x28>)
10: f7ff fffe bl 0 <eq_float_floatarr>
10: R_ARM_THM_CALL aux_arr_eq_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <eq_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <eq_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <eq_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <eq_float_floatarr>
10: R_ARM_THM_CALL aux_arr_eq_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <eq_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <eq_float_floatarr>
28: R_ARM_THM_CALL aux_arr_eq_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <eq_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <eq_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <eq_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <eq_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <eq_float_floatarr+0x28>)
10: f7ff fffe bl 0 <eq_float_floatarr>
10: R_ARM_THM_CALL aux_arr_eq_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <eq_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <eq_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <eq_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_sv
28: 000080e7 jalr ra # 24 <eq_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_float_floatarr+0x30>
riscv64#
0000000000000000 <eq_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <eq_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <eq_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_eq_float_float_sv
28: 000080e7 jalr ra # 24 <eq_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <eq_float_floatarr+0x30>
tricore#
00000000 <eq_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <eq_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <eq_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <eq_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <eq_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <eq_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_eq_float_float_sv
26: 1d 00 00 00 j 26 <eq_float_floatarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <eq_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <eq_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_eq_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <eq_float_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <eq_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <eq_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <eq_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <eq_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <eq_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <eq_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_eq_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ne_intarr_intarr#
STENCIL void ne_intarr_intarr(void) {
// Element-wise ne of int array and int array
aux_arr_ne_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_ne_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ne_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ne_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ne_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ne_intarr_intarr+0x30>
18: ebfffffe bl 0 <ne_intarr_intarr>
18: R_ARM_CALL aux_arr_ne_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ne_intarr_intarr>
28: R_ARM_CALL aux_arr_ne_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ne_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_ne_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_vv
28: 000080e7 jalr ra # 24 <ne_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_intarr+0x30>
riscv64#
0000000000000000 <ne_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_vv
28: 000080e7 jalr ra # 24 <ne_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_intarr+0x30>
tricore#
00000000 <ne_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ne_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_int_int_vv
24: 1d 00 00 00 j 24 <ne_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ne_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_ne_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ne_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ne_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ne_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ne_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ne_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_ne_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ne_intarr_int#
STENCIL void ne_intarr_int(void) {
// Element-wise ne of int array and int scalar
aux_arr_ne_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_intarr_int>
28: R_AARCH64_CALL26 aux_arr_ne_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <ne_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ne_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_intarr_int+0x34>
1c: ebfffffe bl 0 <ne_intarr_int>
1c: R_ARM_CALL aux_arr_ne_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <ne_intarr_int>
2c: R_ARM_CALL aux_arr_ne_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_intarr_int+0x28>)
e: f7ff fffe bl 0 <ne_intarr_int>
e: R_ARM_THM_CALL aux_arr_ne_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <ne_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <ne_intarr_int>
e: R_ARM_THM_CALL aux_arr_ne_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ne_intarr_int>
26: R_ARM_THM_CALL aux_arr_ne_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ne_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_intarr_int+0x28>)
e: f7ff fffe bl 0 <ne_intarr_int>
e: R_ARM_THM_CALL aux_arr_ne_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <ne_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_vs
28: 000080e7 jalr ra # 24 <ne_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_int+0x30>
riscv64#
0000000000000000 <ne_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <ne_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_vs
28: 000080e7 jalr ra # 24 <ne_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_int+0x30>
tricore#
00000000 <ne_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_ne_int_int_vs
24: 1d 00 00 00 j 24 <ne_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_ne_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ne_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ne_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <ne_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <ne_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_ne_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ne_int_intarr#
STENCIL void ne_int_intarr(void) {
// Element-wise ne of int scalar and int array
aux_arr_ne_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ne_int_intarr>
28: R_AARCH64_CALL26 aux_arr_ne_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <ne_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ne_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <ne_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <ne_int_intarr>
1c: R_ARM_CALL aux_arr_ne_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ne_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <ne_int_intarr>
2c: R_ARM_CALL aux_arr_ne_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_intarr>
e: R_ARM_THM_CALL aux_arr_ne_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ne_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_intarr>
e: R_ARM_THM_CALL aux_arr_ne_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ne_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ne_int_intarr>
26: R_ARM_THM_CALL aux_arr_ne_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ne_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_intarr>
e: R_ARM_THM_CALL aux_arr_ne_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ne_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <ne_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_sv
28: 000080e7 jalr ra # 24 <ne_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_int_intarr+0x30>
riscv64#
0000000000000000 <ne_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <ne_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_int_sv
28: 000080e7 jalr ra # 24 <ne_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_int_intarr+0x30>
tricore#
00000000 <ne_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <ne_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_int_int_sv
24: 1d 00 00 00 j 24 <ne_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_ne_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ne_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ne_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <ne_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <ne_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_ne_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ne_intarr_floatarr#
STENCIL void ne_intarr_floatarr(void) {
// Element-wise ne of int array and float array
aux_arr_ne_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_ne_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ne_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ne_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ne_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ne_intarr_floatarr+0x30>
18: ebfffffe bl 0 <ne_intarr_floatarr>
18: R_ARM_CALL aux_arr_ne_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ne_intarr_floatarr>
28: R_ARM_CALL aux_arr_ne_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ne_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_ne_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_vv
28: 000080e7 jalr ra # 24 <ne_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_floatarr+0x30>
riscv64#
0000000000000000 <ne_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_vv
28: 000080e7 jalr ra # 24 <ne_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_floatarr+0x30>
tricore#
00000000 <ne_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ne_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_int_float_vv
24: 1d 00 00 00 j 24 <ne_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ne_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_ne_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ne_intarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ne_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ne_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ne_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ne_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_ne_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ne_intarr_float#
STENCIL void ne_intarr_float(void) {
// Element-wise ne of int array and float scalar
aux_arr_ne_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_intarr_float>
28: R_AARCH64_CALL26 aux_arr_ne_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ne_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ne_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_intarr_float+0x34>
1c: ebfffffe bl 0 <ne_intarr_float>
1c: R_ARM_CALL aux_arr_ne_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ne_intarr_float>
2c: R_ARM_CALL aux_arr_ne_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_intarr_float+0x28>)
10: f7ff fffe bl 0 <ne_intarr_float>
10: R_ARM_THM_CALL aux_arr_ne_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ne_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ne_intarr_float>
10: R_ARM_THM_CALL aux_arr_ne_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ne_intarr_float>
28: R_ARM_THM_CALL aux_arr_ne_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_intarr_float+0x28>)
10: f7ff fffe bl 0 <ne_intarr_float>
10: R_ARM_THM_CALL aux_arr_ne_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ne_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <ne_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_vs
28: 000080e7 jalr ra # 24 <ne_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_float+0x30>
riscv64#
0000000000000000 <ne_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ne_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <ne_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_vs
28: 000080e7 jalr ra # 24 <ne_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_intarr_float+0x30>
tricore#
00000000 <ne_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ne_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <ne_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_ne_int_float_vs
26: 1d 00 00 00 j 26 <ne_intarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_ne_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_intarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ne_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ne_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ne_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <ne_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_ne_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ne_int_floatarr#
STENCIL void ne_int_floatarr(void) {
// Element-wise ne of int scalar and float array
aux_arr_ne_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ne_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_ne_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <ne_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ne_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <ne_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <ne_int_floatarr>
1c: R_ARM_CALL aux_arr_ne_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ne_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <ne_int_floatarr>
2c: R_ARM_CALL aux_arr_ne_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ne_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ne_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ne_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ne_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ne_int_floatarr>
26: R_ARM_THM_CALL aux_arr_ne_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ne_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <ne_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <ne_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <ne_int_floatarr>
e: R_ARM_THM_CALL aux_arr_ne_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ne_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <ne_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_sv
28: 000080e7 jalr ra # 24 <ne_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_int_floatarr+0x30>
riscv64#
0000000000000000 <ne_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <ne_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_int_float_sv
28: 000080e7 jalr ra # 24 <ne_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_int_floatarr+0x30>
tricore#
00000000 <ne_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <ne_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_int_float_sv
24: 1d 00 00 00 j 24 <ne_int_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_ne_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_int_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ne_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ne_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <ne_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <ne_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_ne_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ne_floatarr_intarr#
STENCIL void ne_floatarr_intarr(void) {
// Element-wise ne of float array and int array
aux_arr_ne_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_ne_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ne_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ne_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ne_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ne_floatarr_intarr+0x30>
18: ebfffffe bl 0 <ne_floatarr_intarr>
18: R_ARM_CALL aux_arr_ne_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ne_floatarr_intarr>
28: R_ARM_CALL aux_arr_ne_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ne_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_ne_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_ne_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_vv
28: 000080e7 jalr ra # 24 <ne_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_intarr+0x30>
riscv64#
0000000000000000 <ne_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_vv
28: 000080e7 jalr ra # 24 <ne_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_intarr+0x30>
tricore#
00000000 <ne_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ne_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_float_int_vv
24: 1d 00 00 00 j 24 <ne_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ne_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_ne_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ne_floatarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ne_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ne_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ne_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ne_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_ne_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ne_floatarr_int#
STENCIL void ne_floatarr_int(void) {
// Element-wise ne of float array and int scalar
aux_arr_ne_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_ne_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <ne_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <ne_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_floatarr_int+0x34>
1c: ebfffffe bl 0 <ne_floatarr_int>
1c: R_ARM_CALL aux_arr_ne_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <ne_floatarr_int>
2c: R_ARM_CALL aux_arr_ne_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_floatarr_int+0x28>)
e: f7ff fffe bl 0 <ne_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ne_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <ne_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <ne_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ne_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <ne_floatarr_int>
26: R_ARM_THM_CALL aux_arr_ne_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <ne_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <ne_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <ne_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_floatarr_int+0x28>)
e: f7ff fffe bl 0 <ne_floatarr_int>
e: R_ARM_THM_CALL aux_arr_ne_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <ne_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_vs
28: 000080e7 jalr ra # 24 <ne_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_int+0x30>
riscv64#
0000000000000000 <ne_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <ne_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_vs
28: 000080e7 jalr ra # 24 <ne_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_int+0x30>
tricore#
00000000 <ne_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_ne_float_int_vs
24: 1d 00 00 00 j 24 <ne_floatarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_ne_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_floatarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <ne_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <ne_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <ne_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <ne_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_ne_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
ne_float_intarr#
STENCIL void ne_float_intarr(void) {
// Element-wise ne of float scalar and int array
aux_arr_ne_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ne_float_intarr>
28: R_AARCH64_CALL26 aux_arr_ne_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ne_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ne_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_float_intarr+0x34>
1c: ebfffffe bl 0 <ne_float_intarr>
1c: R_ARM_CALL aux_arr_ne_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ne_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ne_float_intarr>
2c: R_ARM_CALL aux_arr_ne_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_float_intarr+0x28>)
10: f7ff fffe bl 0 <ne_float_intarr>
10: R_ARM_THM_CALL aux_arr_ne_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ne_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ne_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ne_float_intarr>
10: R_ARM_THM_CALL aux_arr_ne_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ne_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ne_float_intarr>
28: R_ARM_THM_CALL aux_arr_ne_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_float_intarr+0x28>)
10: f7ff fffe bl 0 <ne_float_intarr>
10: R_ARM_THM_CALL aux_arr_ne_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ne_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ne_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <ne_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_sv
28: 000080e7 jalr ra # 24 <ne_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_float_intarr+0x30>
riscv64#
0000000000000000 <ne_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ne_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <ne_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_int_sv
28: 000080e7 jalr ra # 24 <ne_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_float_intarr+0x30>
tricore#
00000000 <ne_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ne_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <ne_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_ne_float_int_sv
26: 1d 00 00 00 j 26 <ne_float_intarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_ne_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_float_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ne_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ne_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ne_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <ne_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_ne_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ne_floatarr_floatarr#
STENCIL void ne_floatarr_floatarr(void) {
// Element-wise ne of float array and float array
aux_arr_ne_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_ne_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <ne_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <ne_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <ne_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <ne_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <ne_floatarr_floatarr>
18: R_ARM_CALL aux_arr_ne_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <ne_floatarr_floatarr>
28: R_ARM_CALL aux_arr_ne_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <ne_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_ne_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <ne_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <ne_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <ne_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <ne_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <ne_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_ne_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <ne_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_vv
28: 000080e7 jalr ra # 24 <ne_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <ne_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <ne_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_vv
28: 000080e7 jalr ra # 24 <ne_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_floatarr+0x30>
tricore#
00000000 <ne_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <ne_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <ne_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <ne_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_ne_float_float_vv
24: 1d 00 00 00 j 24 <ne_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <ne_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_ne_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <ne_floatarr_floatarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <ne_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <ne_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <ne_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <ne_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_ne_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
ne_floatarr_float#
STENCIL void ne_floatarr_float(void) {
// Element-wise ne of float array and float scalar
aux_arr_ne_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <ne_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_ne_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ne_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ne_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_floatarr_float+0x34>
1c: ebfffffe bl 0 <ne_floatarr_float>
1c: R_ARM_CALL aux_arr_ne_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <ne_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ne_floatarr_float>
2c: R_ARM_CALL aux_arr_ne_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_floatarr_float+0x28>)
10: f7ff fffe bl 0 <ne_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ne_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <ne_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ne_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ne_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ne_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <ne_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ne_floatarr_float>
28: R_ARM_THM_CALL aux_arr_ne_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_floatarr_float+0x28>)
10: f7ff fffe bl 0 <ne_floatarr_float>
10: R_ARM_THM_CALL aux_arr_ne_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <ne_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ne_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <ne_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_vs
28: 000080e7 jalr ra # 24 <ne_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_float+0x30>
riscv64#
0000000000000000 <ne_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ne_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <ne_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_vs
28: 000080e7 jalr ra # 24 <ne_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_floatarr_float+0x30>
tricore#
00000000 <ne_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ne_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <ne_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_ne_float_float_vs
26: 1d 00 00 00 j 26 <ne_floatarr_float+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_ne_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_floatarr_float+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ne_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ne_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ne_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <ne_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_ne_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
ne_float_floatarr#
STENCIL void ne_float_floatarr(void) {
// Element-wise ne of float scalar and float array
aux_arr_ne_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <ne_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <ne_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_ne_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <ne_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <ne_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <ne_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <ne_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <ne_float_floatarr+0x34>
1c: ebfffffe bl 0 <ne_float_floatarr>
1c: R_ARM_CALL aux_arr_ne_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <ne_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <ne_float_floatarr>
2c: R_ARM_CALL aux_arr_ne_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <ne_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_float_floatarr+0x28>)
10: f7ff fffe bl 0 <ne_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ne_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <ne_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <ne_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <ne_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <ne_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ne_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <ne_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <ne_float_floatarr>
28: R_ARM_THM_CALL aux_arr_ne_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_int_ref>
30: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <ne_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <ne_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <ne_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <ne_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <ne_float_floatarr+0x28>)
10: f7ff fffe bl 0 <ne_float_floatarr>
10: R_ARM_THM_CALL aux_arr_ne_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_int_ref>
18: R_ARM_THM_JUMP24 result_int_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <ne_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <ne_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <ne_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_sv
28: 000080e7 jalr ra # 24 <ne_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_float_floatarr+0x30>
riscv64#
0000000000000000 <ne_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <ne_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <ne_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_ne_float_float_sv
28: 000080e7 jalr ra # 24 <ne_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <ne_float_floatarr+0x30>
tricore#
00000000 <ne_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <ne_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <ne_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <ne_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <ne_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <ne_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_ne_float_float_sv
26: 1d 00 00 00 j 26 <ne_float_floatarr+0x26>
26: R_TRICORE_24REL result_int_ref
x86#
00000000 <ne_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <ne_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_ne_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <ne_float_floatarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <ne_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <ne_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <ne_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <ne_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <ne_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <ne_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_ne_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_int_ref-0x4
pow_intarr_intarr#
STENCIL void pow_intarr_intarr(void) {
// Element-wise pow of int array and int array
aux_arr_pow_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <pow_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_pow_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <pow_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <pow_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <pow_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <pow_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <pow_intarr_intarr+0x30>
18: ebfffffe bl 0 <pow_intarr_intarr>
18: R_ARM_CALL aux_arr_pow_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_int_ref>
20: R_ARM_JUMP24 result_int_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <pow_intarr_intarr>
28: R_ARM_CALL aux_arr_pow_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_int_ref>
30: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <pow_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <pow_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_pow_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_int_ref>
2c: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <pow_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_int_ref>
14: R_ARM_THM_JUMP24 result_int_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_vv
28: 000080e7 jalr ra # 24 <pow_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_intarr_intarr+0x30>
riscv64#
0000000000000000 <pow_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_vv
28: 000080e7 jalr ra # 24 <pow_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_intarr_intarr+0x30>
tricore#
00000000 <pow_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <pow_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_int_int_vv
24: 1d 00 00 00 j 24 <pow_intarr_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <pow_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <pow_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_pow_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <pow_intarr_intarr+0x21>
21: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <pow_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <pow_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <pow_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <pow_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <pow_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_pow_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_int_ref-0x4
pow_intarr_int#
STENCIL void pow_intarr_int(void) {
// Element-wise pow of int array and int scalar
aux_arr_pow_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <pow_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_intarr_int>
28: R_AARCH64_CALL26 aux_arr_pow_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <pow_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <pow_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <pow_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_intarr_int+0x34>
1c: ebfffffe bl 0 <pow_intarr_int>
1c: R_ARM_CALL aux_arr_pow_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <pow_intarr_int>
2c: R_ARM_CALL aux_arr_pow_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <pow_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_intarr_int+0x28>)
e: f7ff fffe bl 0 <pow_intarr_int>
e: R_ARM_THM_CALL aux_arr_pow_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <pow_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <pow_intarr_int>
e: R_ARM_THM_CALL aux_arr_pow_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <pow_intarr_int>
26: R_ARM_THM_CALL aux_arr_pow_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <pow_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_intarr_int+0x28>)
e: f7ff fffe bl 0 <pow_intarr_int>
e: R_ARM_THM_CALL aux_arr_pow_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <pow_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_vs
28: 000080e7 jalr ra # 24 <pow_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_intarr_int+0x30>
riscv64#
0000000000000000 <pow_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <pow_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_vs
28: 000080e7 jalr ra # 24 <pow_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_intarr_int+0x30>
tricore#
00000000 <pow_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_pow_int_int_vs
24: 1d 00 00 00 j 24 <pow_intarr_int+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <pow_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_pow_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_intarr_int+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <pow_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <pow_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <pow_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <pow_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <pow_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_pow_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
pow_int_intarr#
STENCIL void pow_int_intarr(void) {
// Element-wise pow of int scalar and int array
aux_arr_pow_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_int_ref();
}
arm64#
0000000000000000 <pow_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <pow_int_intarr>
28: R_AARCH64_CALL26 aux_arr_pow_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_int_ref>
30: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <pow_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <pow_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <pow_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <pow_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <pow_int_intarr>
1c: R_ARM_CALL aux_arr_pow_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_int_ref>
24: R_ARM_JUMP24 result_int_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <pow_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <pow_int_intarr>
2c: R_ARM_CALL aux_arr_pow_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_int_ref>
34: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <pow_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_intarr>
e: R_ARM_THM_CALL aux_arr_pow_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <pow_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_intarr>
e: R_ARM_THM_CALL aux_arr_pow_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <pow_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <pow_int_intarr>
26: R_ARM_THM_CALL aux_arr_pow_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_int_ref>
2e: R_ARM_THM_JUMP24 result_int_ref
32: bf00 nop
armv81mthumb#
00000000 <pow_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_intarr>
e: R_ARM_THM_CALL aux_arr_pow_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_int_ref>
16: R_ARM_THM_JUMP24 result_int_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <pow_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <pow_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_sv
28: 000080e7 jalr ra # 24 <pow_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_int_intarr+0x30>
riscv64#
0000000000000000 <pow_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <pow_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_int_sv
28: 000080e7 jalr ra # 24 <pow_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_int_ref
34: 00030067 jr t1 # 30 <pow_int_intarr+0x30>
tricore#
00000000 <pow_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <pow_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_int_int_sv
24: 1d 00 00 00 j 24 <pow_int_intarr+0x24>
24: R_TRICORE_24REL result_int_ref
x86#
00000000 <pow_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_pow_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_int_intarr+0x22>
22: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <pow_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <pow_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <pow_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <pow_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <pow_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_pow_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_int_ref-0x4
pow_intarr_floatarr#
STENCIL void pow_intarr_floatarr(void) {
// Element-wise pow of int array and float array
aux_arr_pow_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_pow_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <pow_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <pow_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <pow_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <pow_intarr_floatarr+0x30>
18: ebfffffe bl 0 <pow_intarr_floatarr>
18: R_ARM_CALL aux_arr_pow_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <pow_intarr_floatarr>
28: R_ARM_CALL aux_arr_pow_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <pow_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_pow_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_vv
28: 000080e7 jalr ra # 24 <pow_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_intarr_floatarr+0x30>
riscv64#
0000000000000000 <pow_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_vv
28: 000080e7 jalr ra # 24 <pow_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_intarr_floatarr+0x30>
tricore#
00000000 <pow_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <pow_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_int_float_vv
24: 1d 00 00 00 j 24 <pow_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <pow_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_pow_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <pow_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <pow_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <pow_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <pow_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <pow_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_pow_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
pow_intarr_float#
STENCIL void pow_intarr_float(void) {
// Element-wise pow of int array and float scalar
aux_arr_pow_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_intarr_float>
28: R_AARCH64_CALL26 aux_arr_pow_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <pow_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <pow_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_intarr_float+0x34>
1c: ebfffffe bl 0 <pow_intarr_float>
1c: R_ARM_CALL aux_arr_pow_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <pow_intarr_float>
2c: R_ARM_CALL aux_arr_pow_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_intarr_float+0x28>)
10: f7ff fffe bl 0 <pow_intarr_float>
10: R_ARM_THM_CALL aux_arr_pow_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <pow_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <pow_intarr_float>
10: R_ARM_THM_CALL aux_arr_pow_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <pow_intarr_float>
28: R_ARM_THM_CALL aux_arr_pow_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_intarr_float+0x28>)
10: f7ff fffe bl 0 <pow_intarr_float>
10: R_ARM_THM_CALL aux_arr_pow_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <pow_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <pow_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_vs
28: 000080e7 jalr ra # 24 <pow_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_intarr_float+0x30>
riscv64#
0000000000000000 <pow_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <pow_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <pow_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_vs
28: 000080e7 jalr ra # 24 <pow_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_intarr_float+0x30>
tricore#
00000000 <pow_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <pow_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <pow_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_pow_int_float_vs
26: 1d 00 00 00 j 26 <pow_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_pow_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <pow_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <pow_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <pow_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <pow_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_pow_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
pow_int_floatarr#
STENCIL void pow_int_floatarr(void) {
// Element-wise pow of int scalar and float array
aux_arr_pow_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <pow_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_pow_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <pow_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <pow_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <pow_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <pow_int_floatarr>
1c: R_ARM_CALL aux_arr_pow_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <pow_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <pow_int_floatarr>
2c: R_ARM_CALL aux_arr_pow_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_floatarr>
e: R_ARM_THM_CALL aux_arr_pow_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <pow_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_floatarr>
e: R_ARM_THM_CALL aux_arr_pow_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <pow_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <pow_int_floatarr>
26: R_ARM_THM_CALL aux_arr_pow_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <pow_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <pow_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <pow_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <pow_int_floatarr>
e: R_ARM_THM_CALL aux_arr_pow_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <pow_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <pow_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_sv
28: 000080e7 jalr ra # 24 <pow_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_int_floatarr+0x30>
riscv64#
0000000000000000 <pow_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <pow_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_int_float_sv
28: 000080e7 jalr ra # 24 <pow_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_int_floatarr+0x30>
tricore#
00000000 <pow_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <pow_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_int_float_sv
24: 1d 00 00 00 j 24 <pow_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_pow_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <pow_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <pow_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <pow_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <pow_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_pow_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
pow_floatarr_intarr#
STENCIL void pow_floatarr_intarr(void) {
// Element-wise pow of float array and int array
aux_arr_pow_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_pow_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <pow_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <pow_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <pow_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <pow_floatarr_intarr+0x30>
18: ebfffffe bl 0 <pow_floatarr_intarr>
18: R_ARM_CALL aux_arr_pow_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <pow_floatarr_intarr>
28: R_ARM_CALL aux_arr_pow_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <pow_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_pow_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_pow_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_vv
28: 000080e7 jalr ra # 24 <pow_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_intarr+0x30>
riscv64#
0000000000000000 <pow_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_vv
28: 000080e7 jalr ra # 24 <pow_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_intarr+0x30>
tricore#
00000000 <pow_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <pow_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_float_int_vv
24: 1d 00 00 00 j 24 <pow_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <pow_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_pow_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <pow_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <pow_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <pow_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <pow_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <pow_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_pow_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
pow_floatarr_int#
STENCIL void pow_floatarr_int(void) {
// Element-wise pow of float array and int scalar
aux_arr_pow_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_pow_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <pow_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <pow_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_floatarr_int+0x34>
1c: ebfffffe bl 0 <pow_floatarr_int>
1c: R_ARM_CALL aux_arr_pow_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <pow_floatarr_int>
2c: R_ARM_CALL aux_arr_pow_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_floatarr_int+0x28>)
e: f7ff fffe bl 0 <pow_floatarr_int>
e: R_ARM_THM_CALL aux_arr_pow_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <pow_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <pow_floatarr_int>
e: R_ARM_THM_CALL aux_arr_pow_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <pow_floatarr_int>
26: R_ARM_THM_CALL aux_arr_pow_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <pow_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <pow_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <pow_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_floatarr_int+0x28>)
e: f7ff fffe bl 0 <pow_floatarr_int>
e: R_ARM_THM_CALL aux_arr_pow_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <pow_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_vs
28: 000080e7 jalr ra # 24 <pow_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_int+0x30>
riscv64#
0000000000000000 <pow_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <pow_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_vs
28: 000080e7 jalr ra # 24 <pow_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_int+0x30>
tricore#
00000000 <pow_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_pow_float_int_vs
24: 1d 00 00 00 j 24 <pow_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_pow_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <pow_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <pow_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <pow_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <pow_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_pow_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
pow_float_intarr#
STENCIL void pow_float_intarr(void) {
// Element-wise pow of float scalar and int array
aux_arr_pow_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <pow_float_intarr>
28: R_AARCH64_CALL26 aux_arr_pow_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <pow_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <pow_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_float_intarr+0x34>
1c: ebfffffe bl 0 <pow_float_intarr>
1c: R_ARM_CALL aux_arr_pow_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <pow_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <pow_float_intarr>
2c: R_ARM_CALL aux_arr_pow_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_float_intarr+0x28>)
10: f7ff fffe bl 0 <pow_float_intarr>
10: R_ARM_THM_CALL aux_arr_pow_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <pow_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <pow_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <pow_float_intarr>
10: R_ARM_THM_CALL aux_arr_pow_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <pow_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <pow_float_intarr>
28: R_ARM_THM_CALL aux_arr_pow_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_float_intarr+0x28>)
10: f7ff fffe bl 0 <pow_float_intarr>
10: R_ARM_THM_CALL aux_arr_pow_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <pow_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <pow_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <pow_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_sv
28: 000080e7 jalr ra # 24 <pow_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_float_intarr+0x30>
riscv64#
0000000000000000 <pow_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <pow_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <pow_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_int_sv
28: 000080e7 jalr ra # 24 <pow_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_float_intarr+0x30>
tricore#
00000000 <pow_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <pow_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <pow_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_pow_float_int_sv
26: 1d 00 00 00 j 26 <pow_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_pow_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <pow_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <pow_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <pow_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <pow_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_pow_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
pow_floatarr_floatarr#
STENCIL void pow_floatarr_floatarr(void) {
// Element-wise pow of float array and float array
aux_arr_pow_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_pow_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <pow_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <pow_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <pow_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <pow_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <pow_floatarr_floatarr>
18: R_ARM_CALL aux_arr_pow_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <pow_floatarr_floatarr>
28: R_ARM_CALL aux_arr_pow_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <pow_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_pow_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <pow_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <pow_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <pow_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <pow_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <pow_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_pow_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <pow_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_vv
28: 000080e7 jalr ra # 24 <pow_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <pow_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <pow_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_vv
28: 000080e7 jalr ra # 24 <pow_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_floatarr+0x30>
tricore#
00000000 <pow_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <pow_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <pow_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <pow_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_pow_float_float_vv
24: 1d 00 00 00 j 24 <pow_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <pow_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_pow_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <pow_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <pow_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <pow_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <pow_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <pow_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_pow_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
pow_floatarr_float#
STENCIL void pow_floatarr_float(void) {
// Element-wise pow of float array and float scalar
aux_arr_pow_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <pow_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_pow_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <pow_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <pow_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_floatarr_float+0x34>
1c: ebfffffe bl 0 <pow_floatarr_float>
1c: R_ARM_CALL aux_arr_pow_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <pow_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <pow_floatarr_float>
2c: R_ARM_CALL aux_arr_pow_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_floatarr_float+0x28>)
10: f7ff fffe bl 0 <pow_floatarr_float>
10: R_ARM_THM_CALL aux_arr_pow_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <pow_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <pow_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <pow_floatarr_float>
10: R_ARM_THM_CALL aux_arr_pow_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <pow_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <pow_floatarr_float>
28: R_ARM_THM_CALL aux_arr_pow_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_floatarr_float+0x28>)
10: f7ff fffe bl 0 <pow_floatarr_float>
10: R_ARM_THM_CALL aux_arr_pow_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <pow_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <pow_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <pow_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_vs
28: 000080e7 jalr ra # 24 <pow_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_float+0x30>
riscv64#
0000000000000000 <pow_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <pow_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <pow_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_vs
28: 000080e7 jalr ra # 24 <pow_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_floatarr_float+0x30>
tricore#
00000000 <pow_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <pow_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <pow_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_pow_float_float_vs
26: 1d 00 00 00 j 26 <pow_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_pow_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <pow_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <pow_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <pow_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <pow_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_pow_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
pow_float_floatarr#
STENCIL void pow_float_floatarr(void) {
// Element-wise pow of float scalar and float array
aux_arr_pow_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <pow_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <pow_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_pow_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <pow_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <pow_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <pow_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <pow_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <pow_float_floatarr+0x34>
1c: ebfffffe bl 0 <pow_float_floatarr>
1c: R_ARM_CALL aux_arr_pow_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <pow_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <pow_float_floatarr>
2c: R_ARM_CALL aux_arr_pow_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <pow_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_float_floatarr+0x28>)
10: f7ff fffe bl 0 <pow_float_floatarr>
10: R_ARM_THM_CALL aux_arr_pow_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <pow_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <pow_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <pow_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <pow_float_floatarr>
10: R_ARM_THM_CALL aux_arr_pow_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <pow_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <pow_float_floatarr>
28: R_ARM_THM_CALL aux_arr_pow_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <pow_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <pow_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <pow_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <pow_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <pow_float_floatarr+0x28>)
10: f7ff fffe bl 0 <pow_float_floatarr>
10: R_ARM_THM_CALL aux_arr_pow_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <pow_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <pow_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <pow_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_sv
28: 000080e7 jalr ra # 24 <pow_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_float_floatarr+0x30>
riscv64#
0000000000000000 <pow_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <pow_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <pow_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_pow_float_float_sv
28: 000080e7 jalr ra # 24 <pow_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <pow_float_floatarr+0x30>
tricore#
00000000 <pow_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <pow_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <pow_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <pow_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <pow_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <pow_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_pow_float_float_sv
26: 1d 00 00 00 j 26 <pow_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <pow_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <pow_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_pow_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <pow_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <pow_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <pow_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <pow_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <pow_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <pow_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <pow_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_pow_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
atan2_intarr_intarr#
STENCIL void atan2_intarr_intarr(void) {
// Element-wise atan2 of int array and int array
aux_arr_atan2_int_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_intarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_intarr_intarr>
28: R_AARCH64_CALL26 aux_arr_atan2_int_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_intarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <atan2_intarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <atan2_intarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <atan2_intarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <atan2_intarr_intarr+0x30>
18: ebfffffe bl 0 <atan2_intarr_intarr>
18: R_ARM_CALL aux_arr_atan2_int_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_intarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <atan2_intarr_intarr>
28: R_ARM_CALL aux_arr_atan2_int_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_intarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <atan2_intarr_intarr>
24: R_ARM_THM_CALL aux_arr_atan2_int_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_intarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_intarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_intarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_vv
28: 000080e7 jalr ra # 24 <atan2_intarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_intarr+0x30>
riscv64#
0000000000000000 <atan2_intarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_intarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_vv
28: 000080e7 jalr ra # 24 <atan2_intarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_intarr+0x30>
tricore#
00000000 <atan2_intarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_intarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <atan2_intarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_intarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_intarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_intarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_int_int_vv
24: 1d 00 00 00 j 24 <atan2_intarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_intarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <atan2_intarr_intarr+0x19>
19: R_386_PC32 aux_arr_atan2_int_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <atan2_intarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_intarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_intarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <atan2_intarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <atan2_intarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <atan2_intarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <atan2_intarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_atan2_int_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
atan2_intarr_int#
STENCIL void atan2_intarr_int(void) {
// Element-wise atan2 of int array and int scalar
aux_arr_atan2_int_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_intarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_intarr_int>
28: R_AARCH64_CALL26 aux_arr_atan2_int_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_intarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_intarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <atan2_intarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <atan2_intarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_intarr_int+0x34>
1c: ebfffffe bl 0 <atan2_intarr_int>
1c: R_ARM_CALL aux_arr_atan2_int_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_intarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <atan2_intarr_int>
2c: R_ARM_CALL aux_arr_atan2_int_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_intarr_int+0x28>)
e: f7ff fffe bl 0 <atan2_intarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <atan2_intarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <atan2_intarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_intarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <atan2_intarr_int>
26: R_ARM_THM_CALL aux_arr_atan2_int_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <atan2_intarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_intarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_intarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_intarr_int+0x28>)
e: f7ff fffe bl 0 <atan2_intarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_intarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_intarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <atan2_intarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_vs
28: 000080e7 jalr ra # 24 <atan2_intarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_int+0x30>
riscv64#
0000000000000000 <atan2_intarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_intarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <atan2_intarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_vs
28: 000080e7 jalr ra # 24 <atan2_intarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_int+0x30>
tricore#
00000000 <atan2_intarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_intarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_intarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_intarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_intarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_intarr_int+0x20>
20: R_TRICORE_24REL aux_arr_atan2_int_int_vs
24: 1d 00 00 00 j 24 <atan2_intarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_intarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_intarr_int+0x1a>
1a: R_386_PC32 aux_arr_atan2_int_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_intarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_intarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_intarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <atan2_intarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <atan2_intarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <atan2_intarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <atan2_intarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_atan2_int_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
atan2_int_intarr#
STENCIL void atan2_int_intarr(void) {
// Element-wise atan2 of int scalar and int array
aux_arr_atan2_int_int_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_int_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <atan2_int_intarr>
28: R_AARCH64_CALL26 aux_arr_atan2_int_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_int_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_int_intarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <atan2_int_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <atan2_int_intarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <atan2_int_intarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <atan2_int_intarr>
1c: R_ARM_CALL aux_arr_atan2_int_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <atan2_int_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <atan2_int_intarr>
2c: R_ARM_CALL aux_arr_atan2_int_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_intarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <atan2_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_intarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <atan2_int_intarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <atan2_int_intarr>
26: R_ARM_THM_CALL aux_arr_atan2_int_int_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <atan2_int_intarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_intarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_intarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_intarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_intarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_int_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <atan2_int_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_int_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <atan2_int_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_sv
28: 000080e7 jalr ra # 24 <atan2_int_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_int_intarr+0x30>
riscv64#
0000000000000000 <atan2_int_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_int_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <atan2_int_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_int_sv
28: 000080e7 jalr ra # 24 <atan2_int_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_int_intarr+0x30>
tricore#
00000000 <atan2_int_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_int_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_int_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_int_intarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_int_intarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <atan2_int_intarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_int_int_sv
24: 1d 00 00 00 j 24 <atan2_int_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_int_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_int_intarr+0x1a>
1a: R_386_PC32 aux_arr_atan2_int_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_int_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_int_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_int_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <atan2_int_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <atan2_int_intarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <atan2_int_intarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <atan2_int_intarr+0x29>
25: R_X86_64_PLT32 aux_arr_atan2_int_int_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
atan2_intarr_floatarr#
STENCIL void atan2_intarr_floatarr(void) {
// Element-wise atan2 of int array and float array
aux_arr_atan2_int_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_intarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_intarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_atan2_int_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_intarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <atan2_intarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <atan2_intarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <atan2_intarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <atan2_intarr_floatarr+0x30>
18: ebfffffe bl 0 <atan2_intarr_floatarr>
18: R_ARM_CALL aux_arr_atan2_int_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_intarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <atan2_intarr_floatarr>
28: R_ARM_CALL aux_arr_atan2_int_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_intarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <atan2_intarr_floatarr>
24: R_ARM_THM_CALL aux_arr_atan2_int_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_intarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_intarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_intarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_intarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_intarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_intarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_int_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_intarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_intarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_vv
28: 000080e7 jalr ra # 24 <atan2_intarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_floatarr+0x30>
riscv64#
0000000000000000 <atan2_intarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_intarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_vv
28: 000080e7 jalr ra # 24 <atan2_intarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_floatarr+0x30>
tricore#
00000000 <atan2_intarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_intarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <atan2_intarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_intarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_intarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_intarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_int_float_vv
24: 1d 00 00 00 j 24 <atan2_intarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_intarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <atan2_intarr_floatarr+0x19>
19: R_386_PC32 aux_arr_atan2_int_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <atan2_intarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_intarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_intarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <atan2_intarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <atan2_intarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <atan2_intarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <atan2_intarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_atan2_int_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
atan2_intarr_float#
STENCIL void atan2_intarr_float(void) {
// Element-wise atan2 of int array and float scalar
aux_arr_atan2_int_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_intarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_intarr_float>
28: R_AARCH64_CALL26 aux_arr_atan2_int_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_intarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_intarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <atan2_intarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <atan2_intarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_intarr_float+0x34>
1c: ebfffffe bl 0 <atan2_intarr_float>
1c: R_ARM_CALL aux_arr_atan2_int_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_intarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <atan2_intarr_float>
2c: R_ARM_CALL aux_arr_atan2_int_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_intarr_float+0x28>)
10: f7ff fffe bl 0 <atan2_intarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <atan2_intarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_intarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <atan2_intarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_intarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <atan2_intarr_float>
28: R_ARM_THM_CALL aux_arr_atan2_int_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_intarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_intarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_intarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_intarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_intarr_float+0x28>)
10: f7ff fffe bl 0 <atan2_intarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_int_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_intarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <atan2_intarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <atan2_intarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_vs
28: 000080e7 jalr ra # 24 <atan2_intarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_float+0x30>
riscv64#
0000000000000000 <atan2_intarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <atan2_intarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <atan2_intarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_vs
28: 000080e7 jalr ra # 24 <atan2_intarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_intarr_float+0x30>
tricore#
00000000 <atan2_intarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_intarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <atan2_intarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_intarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_intarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <atan2_intarr_float+0x22>
22: R_TRICORE_24REL aux_arr_atan2_int_float_vs
26: 1d 00 00 00 j 26 <atan2_intarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_intarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_intarr_float+0x1a>
1a: R_386_PC32 aux_arr_atan2_int_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_intarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_intarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_intarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <atan2_intarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <atan2_intarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <atan2_intarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <atan2_intarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_atan2_int_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
atan2_int_floatarr#
STENCIL void atan2_int_floatarr(void) {
// Element-wise atan2 of int scalar and float array
aux_arr_atan2_int_float_sv(*(int *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_int_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000000 adrp x0, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400000 ldr w0, [x0]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000001 adrp x1, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000021 add x1, x1, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <atan2_int_floatarr>
28: R_AARCH64_CALL26 aux_arr_atan2_int_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_int_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_int_floatarr+0x28>
4: e59f0020 ldr r0, [pc, #32] @ 2c <atan2_int_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <atan2_int_floatarr+0x30>
10: e5933000 ldr r3, [r3]
14: e59f1018 ldr r1, [pc, #24] @ 34 <atan2_int_floatarr+0x34>
18: e5900000 ldr r0, [r0]
1c: ebfffffe bl 0 <atan2_int_floatarr>
1c: R_ARM_CALL aux_arr_atan2_int_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg0
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <atan2_int_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3000000 movw r0, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3400000 movt r0, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3001000 movw r1, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3401000 movt r1, #0
24: R_ARM_MOVT_ABS ref_arg1
28: e5900000 ldr r0, [r0]
2c: ebfffffe bl 0 <atan2_int_floatarr>
2c: R_ARM_CALL aux_arr_atan2_int_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_floatarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <atan2_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_floatarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <atan2_int_floatarr>:
0: b508 push {r3, lr}
2: f240 0000 movw r0, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg0
6: f2c0 0000 movt r0, #0
6: R_ARM_THM_MOVT_ABS ref_arg0
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6800 ldr r0, [r0, #0]
1c: f240 0100 movw r1, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0100 movt r1, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <atan2_int_floatarr>
26: R_ARM_THM_CALL aux_arr_atan2_int_float_sv
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <atan2_int_floatarr>:
0: b508 push {r3, lr}
2: 4806 ldr r0, [pc, #24] @ (1c <atan2_int_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_int_floatarr+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_int_floatarr+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4907 ldr r1, [pc, #28] @ (28 <atan2_int_floatarr+0x28>)
c: 6800 ldr r0, [r0, #0]
e: f7ff fffe bl 0 <atan2_int_floatarr>
e: R_ARM_THM_CALL aux_arr_atan2_int_float_sv
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg0
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <atan2_int_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_int_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000517 auipc a0,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 00052503 lw a0,0(a0) # 8 <atan2_int_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000597 auipc a1,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00058593 mv a1,a1
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_sv
28: 000080e7 jalr ra # 24 <atan2_int_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_int_floatarr+0x30>
riscv64#
0000000000000000 <atan2_int_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_int_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00052503 lw a0,0(a0) # 1a <atan2_int_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_int_float_sv
28: 000080e7 jalr ra # 24 <atan2_int_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_int_floatarr+0x30>
tricore#
00000000 <atan2_int_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_int_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_int_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg1
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_int_floatarr>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_int_floatarr>>
1c: R_TRICORE_LO2 ref_arg1
20: 6d 00 00 00 call 20 <atan2_int_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_int_float_sv
24: 1d 00 00 00 j 24 <atan2_int_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_int_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_int_floatarr+0x1a>
1a: R_386_PC32 aux_arr_atan2_int_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_int_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_int_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_int_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <atan2_int_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 38 mov (%rax),%edi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <atan2_int_floatarr+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 24 <atan2_int_floatarr+0x24>
20: R_X86_64_PC32 ref_arg1-0x4
24: e8 00 00 00 00 call 29 <atan2_int_floatarr+0x29>
25: R_X86_64_PLT32 aux_arr_atan2_int_float_sv-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
atan2_floatarr_intarr#
STENCIL void atan2_floatarr_intarr(void) {
// Element-wise atan2 of float array and int array
aux_arr_atan2_float_int_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_floatarr_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_floatarr_intarr>
28: R_AARCH64_CALL26 aux_arr_atan2_float_int_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_floatarr_intarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <atan2_floatarr_intarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <atan2_floatarr_intarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <atan2_floatarr_intarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <atan2_floatarr_intarr+0x30>
18: ebfffffe bl 0 <atan2_floatarr_intarr>
18: R_ARM_CALL aux_arr_atan2_float_int_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_floatarr_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <atan2_floatarr_intarr>
28: R_ARM_CALL aux_arr_atan2_float_int_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_floatarr_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <atan2_floatarr_intarr>
24: R_ARM_THM_CALL aux_arr_atan2_float_int_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_floatarr_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_intarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_intarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_intarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_intarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_intarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_int_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_floatarr_intarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_floatarr_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_vv
28: 000080e7 jalr ra # 24 <atan2_floatarr_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_intarr+0x30>
riscv64#
0000000000000000 <atan2_floatarr_intarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_floatarr_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_vv
28: 000080e7 jalr ra # 24 <atan2_floatarr_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_intarr+0x30>
tricore#
00000000 <atan2_floatarr_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_floatarr_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <atan2_floatarr_intarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_floatarr_intarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_floatarr_intarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_floatarr_intarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_float_int_vv
24: 1d 00 00 00 j 24 <atan2_floatarr_intarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_floatarr_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <atan2_floatarr_intarr+0x19>
19: R_386_PC32 aux_arr_atan2_float_int_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <atan2_floatarr_intarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_floatarr_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_floatarr_intarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <atan2_floatarr_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <atan2_floatarr_intarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <atan2_floatarr_intarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <atan2_floatarr_intarr+0x27>
23: R_X86_64_PLT32 aux_arr_atan2_float_int_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
atan2_floatarr_int#
STENCIL void atan2_floatarr_int(void) {
// Element-wise atan2 of float array and int scalar
aux_arr_atan2_float_int_vs(REF(ref_arg0), *(int *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_floatarr_int>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000003 adrp x3, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000001 adrp x1, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400063 ldr w3, [x3]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000002 adrp x2, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: b9400021 ldr w1, [x1]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000042 add x2, x2, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_floatarr_int>
28: R_AARCH64_CALL26 aux_arr_atan2_float_int_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_floatarr_int>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_floatarr_int+0x28>
4: e59f1020 ldr r1, [pc, #32] @ 2c <atan2_floatarr_int+0x2c>
8: e92d4010 push {r4, lr}
c: e59f201c ldr r2, [pc, #28] @ 30 <atan2_floatarr_int+0x30>
10: e5933000 ldr r3, [r3]
14: e5911000 ldr r1, [r1]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_floatarr_int+0x34>
1c: ebfffffe bl 0 <atan2_floatarr_int>
1c: R_ARM_CALL aux_arr_atan2_float_int_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg2
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_floatarr_int>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3001000 movw r1, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3401000 movt r1, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3002000 movw r2, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3402000 movt r2, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5933000 ldr r3, [r3]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: e5911000 ldr r1, [r1]
2c: ebfffffe bl 0 <atan2_floatarr_int>
2c: R_ARM_CALL aux_arr_atan2_float_int_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_floatarr_int+0x28>)
e: f7ff fffe bl 0 <atan2_floatarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 4807 ldr r0, [pc, #28] @ (28 <atan2_floatarr_int+0x28>)
c: 6809 ldr r1, [r1, #0]
e: f7ff fffe bl 0 <atan2_floatarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_floatarr_int>:
0: b508 push {r3, lr}
2: f240 0100 movw r1, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0100 movt r1, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg2
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg2
12: f240 0200 movw r2, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0200 movt r2, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6809 ldr r1, [r1, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: 681b ldr r3, [r3, #0]
26: f7ff fffe bl 0 <atan2_floatarr_int>
26: R_ARM_THM_CALL aux_arr_atan2_float_int_vs
2a: e8bd 4008 ldmia.w sp!, {r3, lr}
2e: f7ff bffe b.w 0 <result_float_ref>
2e: R_ARM_THM_JUMP24 result_float_ref
32: bf00 nop
armv81mthumb#
00000000 <atan2_floatarr_int>:
0: b508 push {r3, lr}
2: 4906 ldr r1, [pc, #24] @ (1c <atan2_floatarr_int+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_int+0x20>)
6: 4a07 ldr r2, [pc, #28] @ (24 <atan2_floatarr_int+0x24>)
8: 681b ldr r3, [r3, #0]
a: 6809 ldr r1, [r1, #0]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_floatarr_int+0x28>)
e: f7ff fffe bl 0 <atan2_floatarr_int>
e: R_ARM_THM_CALL aux_arr_atan2_float_int_vs
12: e8bd 4008 ldmia.w sp!, {r3, lr}
16: f7ff bffe b.w 0 <result_float_ref>
16: R_ARM_THM_JUMP24 result_float_ref
1a: bf00 nop
...
1c: R_ARM_ABS32 ref_arg1
20: R_ARM_ABS32 ref_arg2
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_floatarr_int>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_floatarr_int>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000597 auipc a1,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0005a583 lw a1,0(a1) # 8 <atan2_floatarr_int+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000617 auipc a2,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00060613 mv a2,a2
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_vs
28: 000080e7 jalr ra # 24 <atan2_floatarr_int+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_int+0x30>
riscv64#
0000000000000000 <atan2_floatarr_int>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_floatarr_int+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0005a583 lw a1,0(a1) # 12 <atan2_floatarr_int+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_vs
28: 000080e7 jalr ra # 24 <atan2_floatarr_int+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_int+0x30>
tricore#
00000000 <atan2_floatarr_int>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_floatarr_int>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_floatarr_int>>
c: R_TRICORE_LO2 ref_arg1
10: 91 00 00 50 movh.a %a5,0
10: R_TRICORE_HIADJ ref_out
14: 91 00 00 40 movh.a %a4,0
14: R_TRICORE_HIADJ ref_arg0
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_floatarr_int>>
18: R_TRICORE_LO2 ref_out
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_floatarr_int>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_floatarr_int+0x20>
20: R_TRICORE_24REL aux_arr_atan2_float_int_vs
24: 1d 00 00 00 j 24 <atan2_floatarr_int+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_floatarr_int>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_floatarr_int+0x1a>
1a: R_386_PC32 aux_arr_atan2_float_int_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_floatarr_int+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_floatarr_int>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_floatarr_int+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 0d 00 00 00 00 lea 0x0(%rip),%rcx # 12 <atan2_floatarr_int+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: 8b 30 mov (%rax),%esi
14: 8b 09 mov (%rcx),%ecx
16: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 1d <atan2_floatarr_int+0x1d>
19: R_X86_64_PC32 ref_out-0x4
1d: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 24 <atan2_floatarr_int+0x24>
20: R_X86_64_PC32 ref_arg0-0x4
24: e8 00 00 00 00 call 29 <atan2_floatarr_int+0x29>
25: R_X86_64_PLT32 aux_arr_atan2_float_int_vs-0x4
29: 48 83 c4 08 add $0x8,%rsp
2d: e9 00 00 00 00 jmp 32 <.LC0+0x2>
2e: R_X86_64_PLT32 result_float_ref-0x4
atan2_float_intarr#
STENCIL void atan2_float_intarr(void) {
// Element-wise atan2 of float scalar and int array
aux_arr_atan2_float_int_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_float_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <atan2_float_intarr>
28: R_AARCH64_CALL26 aux_arr_atan2_float_int_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_float_intarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_float_intarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <atan2_float_intarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <atan2_float_intarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_float_intarr+0x34>
1c: ebfffffe bl 0 <atan2_float_intarr>
1c: R_ARM_CALL aux_arr_atan2_float_int_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <atan2_float_intarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <atan2_float_intarr>
2c: R_ARM_CALL aux_arr_atan2_float_int_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_intarr+0x28>)
10: f7ff fffe bl 0 <atan2_float_intarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <atan2_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_intarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <atan2_float_intarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_intarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <atan2_float_intarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <atan2_float_intarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <atan2_float_intarr>
28: R_ARM_THM_CALL aux_arr_atan2_float_int_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_float_intarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_intarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_intarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_float_intarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_intarr+0x28>)
10: f7ff fffe bl 0 <atan2_float_intarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_int_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <atan2_float_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <atan2_float_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <atan2_float_intarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_sv
28: 000080e7 jalr ra # 24 <atan2_float_intarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_float_intarr+0x30>
riscv64#
0000000000000000 <atan2_float_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <atan2_float_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <atan2_float_intarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_int_sv
28: 000080e7 jalr ra # 24 <atan2_float_intarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_float_intarr+0x30>
tricore#
00000000 <atan2_float_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_float_intarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <atan2_float_intarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_float_intarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_float_intarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <atan2_float_intarr+0x22>
22: R_TRICORE_24REL aux_arr_atan2_float_int_sv
26: 1d 00 00 00 j 26 <atan2_float_intarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_float_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_float_intarr+0x1a>
1a: R_386_PC32 aux_arr_atan2_float_int_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_float_intarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_float_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_float_intarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <atan2_float_intarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <atan2_float_intarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <atan2_float_intarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <atan2_float_intarr+0x2b>
27: R_X86_64_PLT32 aux_arr_atan2_float_int_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
atan2_floatarr_floatarr#
STENCIL void atan2_floatarr_floatarr(void) {
// Element-wise atan2 of float array and float array
aux_arr_atan2_float_float_vv(REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_floatarr_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000000 adrp x0, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000002 adrp x2, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400003 ldr w3, [x0]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 91000042 add x2, x2, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000001 adrp x1, 0 <ref_arg1>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
1c: 90000000 adrp x0, 0 <ref_arg0>
1c: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
20: 91000021 add x1, x1, #0x0
20: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_floatarr_floatarr>
28: R_AARCH64_CALL26 aux_arr_atan2_float_float_vv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_floatarr_floatarr>:
0: e59f301c ldr r3, [pc, #28] @ 24 <atan2_floatarr_floatarr+0x24>
4: e92d4010 push {r4, lr}
8: e59f2018 ldr r2, [pc, #24] @ 28 <atan2_floatarr_floatarr+0x28>
c: e59f1018 ldr r1, [pc, #24] @ 2c <atan2_floatarr_floatarr+0x2c>
10: e5933000 ldr r3, [r3]
14: e59f0014 ldr r0, [pc, #20] @ 30 <atan2_floatarr_floatarr+0x30>
18: ebfffffe bl 0 <atan2_floatarr_floatarr>
18: R_ARM_CALL aux_arr_atan2_float_float_vv
1c: e8bd4010 pop {r4, lr}
20: eafffffe b 0 <result_float_ref>
20: R_ARM_JUMP24 result_float_ref
...
24: R_ARM_ABS32 ref_arg2
28: R_ARM_ABS32 ref_out
2c: R_ARM_ABS32 ref_arg1
30: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_floatarr_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e92d4010 push {r4, lr}
c: e3002000 movw r2, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3402000 movt r2, #0
10: R_ARM_MOVT_ABS ref_out
14: e5933000 ldr r3, [r3]
18: e3001000 movw r1, #0
18: R_ARM_MOVW_ABS_NC ref_arg1
1c: e3401000 movt r1, #0
1c: R_ARM_MOVT_ABS ref_arg1
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ebfffffe bl 0 <atan2_floatarr_floatarr>
28: R_ARM_CALL aux_arr_atan2_float_float_vv
2c: e8bd4010 pop {r4, lr}
30: eafffffe b 0 <result_float_ref>
30: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_floatarr_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0200 movw r2, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0200 movt r2, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg1
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_arg1
1a: 681b ldr r3, [r3, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: f7ff fffe bl 0 <atan2_floatarr_floatarr>
24: R_ARM_THM_CALL aux_arr_atan2_float_float_vv
28: e8bd 4008 ldmia.w sp!, {r3, lr}
2c: f7ff bffe b.w 0 <result_float_ref>
2c: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_floatarr_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan2_floatarr_floatarr+0x18>)
4: 4a05 ldr r2, [pc, #20] @ (1c <atan2_floatarr_floatarr+0x1c>)
6: 681b ldr r3, [r3, #0]
8: 4905 ldr r1, [pc, #20] @ (20 <atan2_floatarr_floatarr+0x20>)
a: 4806 ldr r0, [pc, #24] @ (24 <atan2_floatarr_floatarr+0x24>)
c: f7ff fffe bl 0 <atan2_floatarr_floatarr>
c: R_ARM_THM_CALL aux_arr_atan2_float_float_vv
10: e8bd 4008 ldmia.w sp!, {r3, lr}
14: f7ff bffe b.w 0 <result_float_ref>
14: R_ARM_THM_JUMP24 result_float_ref
...
18: R_ARM_ABS32 ref_arg2
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_floatarr_floatarr>:
0: 00000697 auipc a3,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 0006a683 lw a3,0(a3) # 0 <atan2_floatarr_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_vv
28: 000080e7 jalr ra # 24 <atan2_floatarr_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_floatarr+0x30>
riscv64#
0000000000000000 <atan2_floatarr_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000697 auipc a3,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 0006a683 lw a3,0(a3) # 2 <atan2_floatarr_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000617 auipc a2,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00060613 mv a2,a2
e: R_RISCV_PCREL_LO12_I .L0
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_vv
28: 000080e7 jalr ra # 24 <atan2_floatarr_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_floatarr+0x30>
tricore#
00000000 <atan2_floatarr_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan2_floatarr_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 60 movh.a %a6,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 50 movh.a %a5,0
c: R_TRICORE_HIADJ ref_arg1
10: 91 00 00 40 movh.a %a4,0
10: R_TRICORE_HIADJ ref_arg0
14: d9 66 00 00 lea %a6,[%a6]0 <0 <atan2_floatarr_floatarr>>
14: R_TRICORE_LO2 ref_out
18: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_floatarr_floatarr>>
18: R_TRICORE_LO2 ref_arg1
1c: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_floatarr_floatarr>>
1c: R_TRICORE_LO2 ref_arg0
20: 6d 00 00 00 call 20 <atan2_floatarr_floatarr+0x20>
20: R_TRICORE_24REL aux_arr_atan2_float_float_vv
24: 1d 00 00 00 j 24 <atan2_floatarr_floatarr+0x24>
24: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_floatarr_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: 68 00 00 00 00 push $0x0
14: R_386_32 ref_arg0
18: e8 fc ff ff ff call 19 <atan2_floatarr_floatarr+0x19>
19: R_386_PC32 aux_arr_atan2_float_float_vv
1d: 83 c4 1c add $0x1c,%esp
20: e9 fc ff ff ff jmp 21 <atan2_floatarr_floatarr+0x21>
21: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_floatarr_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_floatarr_floatarr+0xb>
7: R_X86_64_PC32 ref_arg2-0x4
b: 8b 08 mov (%rax),%ecx
d: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 14 <atan2_floatarr_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1b <atan2_floatarr_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg1-0x4
1b: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 22 <atan2_floatarr_floatarr+0x22>
1e: R_X86_64_PC32 ref_arg0-0x4
22: e8 00 00 00 00 call 27 <atan2_floatarr_floatarr+0x27>
23: R_X86_64_PLT32 aux_arr_atan2_float_float_vv-0x4
27: 48 83 c4 08 add $0x8,%rsp
2b: e9 00 00 00 00 jmp 30 <.LC0>
2c: R_X86_64_PLT32 result_float_ref-0x4
atan2_floatarr_float#
STENCIL void atan2_floatarr_float(void) {
// Element-wise atan2 of float array and float scalar
aux_arr_atan2_float_float_vs(REF(ref_arg0), *(float *)REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_floatarr_float>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg1>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg0>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
28: 94000000 bl 0 <atan2_floatarr_float>
28: R_AARCH64_CALL26 aux_arr_atan2_float_float_vs
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_floatarr_float>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_floatarr_float+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <atan2_floatarr_float+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <atan2_floatarr_float+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_floatarr_float+0x34>
1c: ebfffffe bl 0 <atan2_floatarr_float>
1c: R_ARM_CALL aux_arr_atan2_float_float_vs
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg1
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan2_floatarr_float>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg1
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg1
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg0
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg0
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <atan2_floatarr_float>
2c: R_ARM_CALL aux_arr_atan2_float_float_vs
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_floatarr_float+0x28>)
10: f7ff fffe bl 0 <atan2_floatarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan2_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_float+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <atan2_floatarr_float+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_floatarr_float+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <atan2_floatarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan2_floatarr_float>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg1
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg1
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg0
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg0
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <atan2_floatarr_float>
28: R_ARM_THM_CALL aux_arr_atan2_float_float_vs
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_floatarr_float>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_floatarr_float+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_floatarr_float+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_floatarr_float+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_floatarr_float+0x28>)
10: f7ff fffe bl 0 <atan2_floatarr_float>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_vs
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan2_floatarr_float>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <atan2_floatarr_float>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg1
c: 0007a507 flw fa0,0(a5) # 8 <atan2_floatarr_float+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_vs
28: 000080e7 jalr ra # 24 <atan2_floatarr_float+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_float+0x30>
riscv64#
0000000000000000 <atan2_floatarr_float>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <atan2_floatarr_float+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000797 auipc a5,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 0007a507 flw fa0,0(a5) # 12 <atan2_floatarr_float+0x12>
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_vs
28: 000080e7 jalr ra # 24 <atan2_floatarr_float+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_floatarr_float+0x30>
tricore#
00000000 <atan2_floatarr_float>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_floatarr_float>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg1
c: d9 22 00 00 lea %a2,[%a2]0 <0 <atan2_floatarr_float>>
c: R_TRICORE_LO2 ref_arg1
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg0
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_floatarr_float>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_floatarr_float>>
1e: R_TRICORE_LO2 ref_arg0
22: 6d 00 00 00 call 22 <atan2_floatarr_float+0x22>
22: R_TRICORE_24REL aux_arr_atan2_float_float_vs
26: 1d 00 00 00 j 26 <atan2_floatarr_float+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_floatarr_float>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: ff 35 00 00 00 00 push 0x0
10: R_386_32 ref_arg1
14: 68 00 00 00 00 push $0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_floatarr_float+0x1a>
1a: R_386_PC32 aux_arr_atan2_float_float_vs
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_floatarr_float+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_floatarr_float>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_floatarr_float+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <atan2_floatarr_float+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <atan2_floatarr_float+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <atan2_floatarr_float+0x26>
22: R_X86_64_PC32 ref_arg0-0x4
26: e8 00 00 00 00 call 2b <atan2_floatarr_float+0x2b>
27: R_X86_64_PLT32 aux_arr_atan2_float_float_vs-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
atan2_float_floatarr#
STENCIL void atan2_float_floatarr(void) {
// Element-wise atan2 of float scalar and float array
aux_arr_atan2_float_float_sv(*(float *)REF(ref_arg0), REF(ref_arg1), REF(ref_out), *(int *)REF(ref_arg2));
result_float_ref();
}
arm64#
0000000000000000 <atan2_float_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg2>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg2
8: 90000003 adrp x3, 0 <ref_arg0>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg2
14: 90000001 adrp x1, 0 <ref_out>
14: R_AARCH64_ADR_PREL_PG_HI21 ref_out
18: bd400060 ldr s0, [x3]
18: R_AARCH64_LDST32_ABS_LO12_NC ref_arg0
1c: 91000021 add x1, x1, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_out
20: 90000000 adrp x0, 0 <ref_arg1>
20: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
24: 91000000 add x0, x0, #0x0
24: R_AARCH64_ADD_ABS_LO12_NC ref_arg1
28: 94000000 bl 0 <atan2_float_floatarr>
28: R_AARCH64_CALL26 aux_arr_atan2_float_float_sv
2c: a8c17bfd ldp x29, x30, [sp], #16
30: 14000000 b 0 <result_float_ref>
30: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan2_float_floatarr>:
0: e59f3020 ldr r3, [pc, #32] @ 28 <atan2_float_floatarr+0x28>
4: e59f2020 ldr r2, [pc, #32] @ 2c <atan2_float_floatarr+0x2c>
8: e92d4010 push {r4, lr}
c: ed930a00 vldr s0, [r3]
10: e59f1018 ldr r1, [pc, #24] @ 30 <atan2_float_floatarr+0x30>
14: e5922000 ldr r2, [r2]
18: e59f0014 ldr r0, [pc, #20] @ 34 <atan2_float_floatarr+0x34>
1c: ebfffffe bl 0 <atan2_float_floatarr>
1c: R_ARM_CALL aux_arr_atan2_float_float_sv
20: e8bd4010 pop {r4, lr}
24: eafffffe b 0 <result_float_ref>
24: R_ARM_JUMP24 result_float_ref
...
28: R_ARM_ABS32 ref_arg0
2c: R_ARM_ABS32 ref_arg2
30: R_ARM_ABS32 ref_out
34: R_ARM_ABS32 ref_arg1
armv7#
00000000 <atan2_float_floatarr>:
0: e3002000 movw r2, #0
0: R_ARM_MOVW_ABS_NC ref_arg2
4: e3402000 movt r2, #0
4: R_ARM_MOVT_ABS ref_arg2
8: e3003000 movw r3, #0
8: R_ARM_MOVW_ABS_NC ref_arg0
c: e3403000 movt r3, #0
c: R_ARM_MOVT_ABS ref_arg0
10: e92d4010 push {r4, lr}
14: e3001000 movw r1, #0
14: R_ARM_MOVW_ABS_NC ref_out
18: e3401000 movt r1, #0
18: R_ARM_MOVT_ABS ref_out
1c: e5922000 ldr r2, [r2]
20: e3000000 movw r0, #0
20: R_ARM_MOVW_ABS_NC ref_arg1
24: e3400000 movt r0, #0
24: R_ARM_MOVT_ABS ref_arg1
28: ed930a00 vldr s0, [r3]
2c: ebfffffe bl 0 <atan2_float_floatarr>
2c: R_ARM_CALL aux_arr_atan2_float_float_sv
30: e8bd4010 pop {r4, lr}
34: eafffffe b 0 <result_float_ref>
34: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan2_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_floatarr+0x28>)
10: f7ff fffe bl 0 <atan2_float_floatarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7mthumb_fpv5#
00000000 <atan2_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_floatarr+0x20>)
6: 4907 ldr r1, [pc, #28] @ (24 <atan2_float_floatarr+0x24>)
8: ed93 0a00 vldr s0, [r3]
c: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_floatarr+0x28>)
e: 6812 ldr r2, [r2, #0]
10: f7ff fffe bl 0 <atan2_float_floatarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
armv7thumb#
00000000 <atan2_float_floatarr>:
0: b508 push {r3, lr}
2: f240 0200 movw r2, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg2
6: f2c0 0200 movt r2, #0
6: R_ARM_THM_MOVT_ABS ref_arg2
a: f240 0300 movw r3, #0
a: R_ARM_THM_MOVW_ABS_NC ref_arg0
e: f2c0 0300 movt r3, #0
e: R_ARM_THM_MOVT_ABS ref_arg0
12: f240 0100 movw r1, #0
12: R_ARM_THM_MOVW_ABS_NC ref_out
16: f2c0 0100 movt r1, #0
16: R_ARM_THM_MOVT_ABS ref_out
1a: 6812 ldr r2, [r2, #0]
1c: f240 0000 movw r0, #0
1c: R_ARM_THM_MOVW_ABS_NC ref_arg1
20: f2c0 0000 movt r0, #0
20: R_ARM_THM_MOVT_ABS ref_arg1
24: ed93 0a00 vldr s0, [r3]
28: f7ff fffe bl 0 <atan2_float_floatarr>
28: R_ARM_THM_CALL aux_arr_atan2_float_float_sv
2c: e8bd 4008 ldmia.w sp!, {r3, lr}
30: f7ff bffe b.w 0 <result_float_ref>
30: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan2_float_floatarr>:
0: b508 push {r3, lr}
2: 4a06 ldr r2, [pc, #24] @ (1c <atan2_float_floatarr+0x1c>)
4: 4b06 ldr r3, [pc, #24] @ (20 <atan2_float_floatarr+0x20>)
6: 6812 ldr r2, [r2, #0]
8: ed93 0a00 vldr s0, [r3]
c: 4905 ldr r1, [pc, #20] @ (24 <atan2_float_floatarr+0x24>)
e: 4806 ldr r0, [pc, #24] @ (28 <atan2_float_floatarr+0x28>)
10: f7ff fffe bl 0 <atan2_float_floatarr>
10: R_ARM_THM_CALL aux_arr_atan2_float_float_sv
14: e8bd 4008 ldmia.w sp!, {r3, lr}
18: f7ff bffe b.w 0 <result_float_ref>
18: R_ARM_THM_JUMP24 result_float_ref
...
1c: R_ARM_ABS32 ref_arg2
20: R_ARM_ABS32 ref_arg0
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg1
riscv32#
00000000 <atan2_float_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg2
4: 00062603 lw a2,0(a2) # 0 <atan2_float_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 00000797 auipc a5,0x0
8: R_RISCV_PCREL_HI20 ref_arg0
c: 0007a507 flw fa0,0(a5) # 8 <atan2_float_floatarr+0x8>
c: R_RISCV_PCREL_LO12_I .L0
10: 1141 addi sp,sp,-16
12: 00000597 auipc a1,0x0
12: R_RISCV_PCREL_HI20 ref_out
16: 00058593 mv a1,a1
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000517 auipc a0,0x0
1a: R_RISCV_PCREL_HI20 ref_arg1
1e: 00050513 mv a0,a0
1e: R_RISCV_PCREL_LO12_I .L0
22: c606 sw ra,12(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_sv
28: 000080e7 jalr ra # 24 <atan2_float_floatarr+0x24>
2c: 40b2 lw ra,12(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_float_floatarr+0x30>
riscv64#
0000000000000000 <atan2_float_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg2
6: 00062603 lw a2,0(a2) # 2 <atan2_float_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg1
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: 00000797 auipc a5,0x0
1a: R_RISCV_PCREL_HI20 ref_arg0
1e: 0007a507 flw fa0,0(a5) # 1a <atan2_float_floatarr+0x1a>
1e: R_RISCV_PCREL_LO12_I .L0
22: e406 sd ra,8(sp)
24: 00000097 auipc ra,0x0
24: R_RISCV_CALL_PLT aux_arr_atan2_float_float_sv
28: 000080e7 jalr ra # 24 <atan2_float_floatarr+0x24>
2c: 60a2 ld ra,8(sp)
2e: 0141 addi sp,sp,16
30: 00000317 auipc t1,0x0
30: R_RISCV_CALL_PLT result_float_ref
34: 00030067 jr t1 # 30 <atan2_float_floatarr+0x30>
tricore#
00000000 <atan2_float_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg2
4: 19 25 00 00 ld.w %d5,[%a2]0 <0 <atan2_float_floatarr>>
4: R_TRICORE_LO2 ref_arg2
8: 91 00 00 20 movh.a %a2,0
8: R_TRICORE_HIADJ ref_arg0
c: d9 22 00 00 lea %a2,[%a2]0 <0 <atan2_float_floatarr>>
c: R_TRICORE_LO2 ref_arg0
10: 54 24 ld.w %d4,[%a2]
12: 91 00 00 50 movh.a %a5,0
12: R_TRICORE_HIADJ ref_out
16: 91 00 00 40 movh.a %a4,0
16: R_TRICORE_HIADJ ref_arg1
1a: d9 55 00 00 lea %a5,[%a5]0 <0 <atan2_float_floatarr>>
1a: R_TRICORE_LO2 ref_out
1e: d9 44 00 00 lea %a4,[%a4]0 <0 <atan2_float_floatarr>>
1e: R_TRICORE_LO2 ref_arg1
22: 6d 00 00 00 call 22 <atan2_float_floatarr+0x22>
22: R_TRICORE_24REL aux_arr_atan2_float_float_sv
26: 1d 00 00 00 j 26 <atan2_float_floatarr+0x26>
26: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan2_float_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg2
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg1
13: ff 35 00 00 00 00 push 0x0
15: R_386_32 ref_arg0
19: e8 fc ff ff ff call 1a <atan2_float_floatarr+0x1a>
1a: R_386_PC32 aux_arr_atan2_float_float_sv
1e: 83 c4 1c add $0x1c,%esp
21: e9 fc ff ff ff jmp 22 <atan2_float_floatarr+0x22>
22: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan2_float_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan2_float_floatarr+0xb>
7: R_X86_64_PC32 ref_arg0-0x4
b: 48 8d 15 00 00 00 00 lea 0x0(%rip),%rdx # 12 <atan2_float_floatarr+0x12>
e: R_X86_64_PC32 ref_arg2-0x4
12: f3 0f 10 00 movss (%rax),%xmm0
16: 8b 12 mov (%rdx),%edx
18: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 1f <atan2_float_floatarr+0x1f>
1b: R_X86_64_PC32 ref_out-0x4
1f: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 26 <atan2_float_floatarr+0x26>
22: R_X86_64_PC32 ref_arg1-0x4
26: e8 00 00 00 00 call 2b <atan2_float_floatarr+0x2b>
27: R_X86_64_PLT32 aux_arr_atan2_float_float_sv-0x4
2b: 48 83 c4 08 add $0x8,%rsp
2f: e9 00 00 00 00 jmp 34 <.LC1>
30: R_X86_64_PLT32 result_float_ref-0x4
sqrt_intarr#
STENCIL void sqrt_intarr(void) {
// Element-wise sqrt of int array
aux_arr_sqrt_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <sqrt_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <sqrt_intarr>
20: R_AARCH64_CALL26 aux_arr_sqrt_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sqrt_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <sqrt_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <sqrt_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <sqrt_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <sqrt_intarr>
14: R_ARM_CALL aux_arr_sqrt_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sqrt_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <sqrt_intarr>
20: R_ARM_CALL aux_arr_sqrt_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sqrt_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_intarr+0x20>)
a: f7ff fffe bl 0 <sqrt_intarr>
a: R_ARM_THM_CALL aux_arr_sqrt_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sqrt_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_intarr+0x20>)
a: f7ff fffe bl 0 <sqrt_intarr>
a: R_ARM_THM_CALL aux_arr_sqrt_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sqrt_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <sqrt_intarr>
1c: R_ARM_THM_CALL aux_arr_sqrt_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sqrt_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_intarr+0x20>)
a: f7ff fffe bl 0 <sqrt_intarr>
a: R_ARM_THM_CALL aux_arr_sqrt_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sqrt_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <sqrt_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sqrt_int
20: 000080e7 jalr ra # 1c <sqrt_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sqrt_intarr+0x28>
riscv64#
0000000000000000 <sqrt_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <sqrt_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sqrt_int
20: 000080e7 jalr ra # 1c <sqrt_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sqrt_intarr+0x28>
tricore#
00000000 <sqrt_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sqrt_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <sqrt_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <sqrt_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <sqrt_intarr+0x18>
18: R_TRICORE_24REL aux_arr_sqrt_int
1c: 1d 00 00 00 j 1c <sqrt_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <sqrt_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <sqrt_intarr+0x14>
14: R_386_PC32 aux_arr_sqrt_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <sqrt_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sqrt_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sqrt_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <sqrt_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <sqrt_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <sqrt_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_sqrt_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
sqrt_floatarr#
STENCIL void sqrt_floatarr(void) {
// Element-wise sqrt of float array
aux_arr_sqrt_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <sqrt_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <sqrt_floatarr>
20: R_AARCH64_CALL26 aux_arr_sqrt_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sqrt_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <sqrt_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <sqrt_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <sqrt_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <sqrt_floatarr>
14: R_ARM_CALL aux_arr_sqrt_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sqrt_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <sqrt_floatarr>
20: R_ARM_CALL aux_arr_sqrt_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sqrt_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_floatarr+0x20>)
a: f7ff fffe bl 0 <sqrt_floatarr>
a: R_ARM_THM_CALL aux_arr_sqrt_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sqrt_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_floatarr+0x20>)
a: f7ff fffe bl 0 <sqrt_floatarr>
a: R_ARM_THM_CALL aux_arr_sqrt_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sqrt_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <sqrt_floatarr>
1c: R_ARM_THM_CALL aux_arr_sqrt_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sqrt_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sqrt_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sqrt_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sqrt_floatarr+0x20>)
a: f7ff fffe bl 0 <sqrt_floatarr>
a: R_ARM_THM_CALL aux_arr_sqrt_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sqrt_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <sqrt_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sqrt_float
20: 000080e7 jalr ra # 1c <sqrt_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sqrt_floatarr+0x28>
riscv64#
0000000000000000 <sqrt_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <sqrt_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sqrt_float
20: 000080e7 jalr ra # 1c <sqrt_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sqrt_floatarr+0x28>
tricore#
00000000 <sqrt_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sqrt_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <sqrt_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <sqrt_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <sqrt_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_sqrt_float
1c: 1d 00 00 00 j 1c <sqrt_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <sqrt_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <sqrt_floatarr+0x14>
14: R_386_PC32 aux_arr_sqrt_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <sqrt_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sqrt_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sqrt_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <sqrt_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <sqrt_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <sqrt_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_sqrt_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
exp_intarr#
STENCIL void exp_intarr(void) {
// Element-wise exp of int array
aux_arr_exp_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <exp_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <exp_intarr>
20: R_AARCH64_CALL26 aux_arr_exp_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <exp_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <exp_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <exp_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <exp_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <exp_intarr>
14: R_ARM_CALL aux_arr_exp_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <exp_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <exp_intarr>
20: R_ARM_CALL aux_arr_exp_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <exp_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_intarr+0x20>)
a: f7ff fffe bl 0 <exp_intarr>
a: R_ARM_THM_CALL aux_arr_exp_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <exp_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_intarr+0x20>)
a: f7ff fffe bl 0 <exp_intarr>
a: R_ARM_THM_CALL aux_arr_exp_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <exp_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <exp_intarr>
1c: R_ARM_THM_CALL aux_arr_exp_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <exp_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_intarr+0x20>)
a: f7ff fffe bl 0 <exp_intarr>
a: R_ARM_THM_CALL aux_arr_exp_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <exp_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <exp_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_exp_int
20: 000080e7 jalr ra # 1c <exp_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <exp_intarr+0x28>
riscv64#
0000000000000000 <exp_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <exp_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_exp_int
20: 000080e7 jalr ra # 1c <exp_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <exp_intarr+0x28>
tricore#
00000000 <exp_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <exp_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <exp_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <exp_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <exp_intarr+0x18>
18: R_TRICORE_24REL aux_arr_exp_int
1c: 1d 00 00 00 j 1c <exp_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <exp_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <exp_intarr+0x14>
14: R_386_PC32 aux_arr_exp_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <exp_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <exp_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <exp_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <exp_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <exp_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <exp_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_exp_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
exp_floatarr#
STENCIL void exp_floatarr(void) {
// Element-wise exp of float array
aux_arr_exp_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <exp_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <exp_floatarr>
20: R_AARCH64_CALL26 aux_arr_exp_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <exp_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <exp_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <exp_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <exp_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <exp_floatarr>
14: R_ARM_CALL aux_arr_exp_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <exp_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <exp_floatarr>
20: R_ARM_CALL aux_arr_exp_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <exp_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_floatarr+0x20>)
a: f7ff fffe bl 0 <exp_floatarr>
a: R_ARM_THM_CALL aux_arr_exp_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <exp_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_floatarr+0x20>)
a: f7ff fffe bl 0 <exp_floatarr>
a: R_ARM_THM_CALL aux_arr_exp_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <exp_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <exp_floatarr>
1c: R_ARM_THM_CALL aux_arr_exp_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <exp_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <exp_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <exp_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <exp_floatarr+0x20>)
a: f7ff fffe bl 0 <exp_floatarr>
a: R_ARM_THM_CALL aux_arr_exp_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <exp_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <exp_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_exp_float
20: 000080e7 jalr ra # 1c <exp_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <exp_floatarr+0x28>
riscv64#
0000000000000000 <exp_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <exp_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_exp_float
20: 000080e7 jalr ra # 1c <exp_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <exp_floatarr+0x28>
tricore#
00000000 <exp_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <exp_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <exp_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <exp_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <exp_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_exp_float
1c: 1d 00 00 00 j 1c <exp_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <exp_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <exp_floatarr+0x14>
14: R_386_PC32 aux_arr_exp_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <exp_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <exp_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <exp_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <exp_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <exp_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <exp_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_exp_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
log_intarr#
STENCIL void log_intarr(void) {
// Element-wise log of int array
aux_arr_log_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <log_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <log_intarr>
20: R_AARCH64_CALL26 aux_arr_log_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <log_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <log_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <log_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <log_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <log_intarr>
14: R_ARM_CALL aux_arr_log_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <log_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <log_intarr>
20: R_ARM_CALL aux_arr_log_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <log_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_intarr+0x20>)
a: f7ff fffe bl 0 <log_intarr>
a: R_ARM_THM_CALL aux_arr_log_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <log_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_intarr+0x20>)
a: f7ff fffe bl 0 <log_intarr>
a: R_ARM_THM_CALL aux_arr_log_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <log_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <log_intarr>
1c: R_ARM_THM_CALL aux_arr_log_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <log_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_intarr+0x20>)
a: f7ff fffe bl 0 <log_intarr>
a: R_ARM_THM_CALL aux_arr_log_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <log_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <log_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_log_int
20: 000080e7 jalr ra # 1c <log_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <log_intarr+0x28>
riscv64#
0000000000000000 <log_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <log_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_log_int
20: 000080e7 jalr ra # 1c <log_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <log_intarr+0x28>
tricore#
00000000 <log_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <log_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <log_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <log_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <log_intarr+0x18>
18: R_TRICORE_24REL aux_arr_log_int
1c: 1d 00 00 00 j 1c <log_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <log_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <log_intarr+0x14>
14: R_386_PC32 aux_arr_log_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <log_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <log_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <log_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <log_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <log_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <log_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_log_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
log_floatarr#
STENCIL void log_floatarr(void) {
// Element-wise log of float array
aux_arr_log_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <log_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <log_floatarr>
20: R_AARCH64_CALL26 aux_arr_log_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <log_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <log_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <log_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <log_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <log_floatarr>
14: R_ARM_CALL aux_arr_log_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <log_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <log_floatarr>
20: R_ARM_CALL aux_arr_log_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <log_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_floatarr+0x20>)
a: f7ff fffe bl 0 <log_floatarr>
a: R_ARM_THM_CALL aux_arr_log_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <log_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_floatarr+0x20>)
a: f7ff fffe bl 0 <log_floatarr>
a: R_ARM_THM_CALL aux_arr_log_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <log_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <log_floatarr>
1c: R_ARM_THM_CALL aux_arr_log_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <log_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <log_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <log_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <log_floatarr+0x20>)
a: f7ff fffe bl 0 <log_floatarr>
a: R_ARM_THM_CALL aux_arr_log_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <log_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <log_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_log_float
20: 000080e7 jalr ra # 1c <log_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <log_floatarr+0x28>
riscv64#
0000000000000000 <log_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <log_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_log_float
20: 000080e7 jalr ra # 1c <log_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <log_floatarr+0x28>
tricore#
00000000 <log_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <log_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <log_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <log_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <log_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_log_float
1c: 1d 00 00 00 j 1c <log_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <log_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <log_floatarr+0x14>
14: R_386_PC32 aux_arr_log_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <log_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <log_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <log_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <log_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <log_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <log_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_log_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
sin_intarr#
STENCIL void sin_intarr(void) {
// Element-wise sin of int array
aux_arr_sin_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <sin_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <sin_intarr>
20: R_AARCH64_CALL26 aux_arr_sin_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sin_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <sin_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <sin_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <sin_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <sin_intarr>
14: R_ARM_CALL aux_arr_sin_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sin_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <sin_intarr>
20: R_ARM_CALL aux_arr_sin_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_intarr+0x20>)
a: f7ff fffe bl 0 <sin_intarr>
a: R_ARM_THM_CALL aux_arr_sin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_intarr+0x20>)
a: f7ff fffe bl 0 <sin_intarr>
a: R_ARM_THM_CALL aux_arr_sin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sin_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <sin_intarr>
1c: R_ARM_THM_CALL aux_arr_sin_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_intarr+0x20>)
a: f7ff fffe bl 0 <sin_intarr>
a: R_ARM_THM_CALL aux_arr_sin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sin_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <sin_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sin_int
20: 000080e7 jalr ra # 1c <sin_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sin_intarr+0x28>
riscv64#
0000000000000000 <sin_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <sin_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sin_int
20: 000080e7 jalr ra # 1c <sin_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sin_intarr+0x28>
tricore#
00000000 <sin_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sin_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <sin_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <sin_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <sin_intarr+0x18>
18: R_TRICORE_24REL aux_arr_sin_int
1c: 1d 00 00 00 j 1c <sin_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <sin_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <sin_intarr+0x14>
14: R_386_PC32 aux_arr_sin_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <sin_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sin_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sin_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <sin_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <sin_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <sin_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_sin_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
sin_floatarr#
STENCIL void sin_floatarr(void) {
// Element-wise sin of float array
aux_arr_sin_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <sin_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <sin_floatarr>
20: R_AARCH64_CALL26 aux_arr_sin_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <sin_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <sin_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <sin_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <sin_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <sin_floatarr>
14: R_ARM_CALL aux_arr_sin_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <sin_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <sin_floatarr>
20: R_ARM_CALL aux_arr_sin_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <sin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_floatarr+0x20>)
a: f7ff fffe bl 0 <sin_floatarr>
a: R_ARM_THM_CALL aux_arr_sin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <sin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_floatarr+0x20>)
a: f7ff fffe bl 0 <sin_floatarr>
a: R_ARM_THM_CALL aux_arr_sin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <sin_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <sin_floatarr>
1c: R_ARM_THM_CALL aux_arr_sin_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <sin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <sin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <sin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <sin_floatarr+0x20>)
a: f7ff fffe bl 0 <sin_floatarr>
a: R_ARM_THM_CALL aux_arr_sin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <sin_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <sin_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sin_float
20: 000080e7 jalr ra # 1c <sin_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sin_floatarr+0x28>
riscv64#
0000000000000000 <sin_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <sin_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_sin_float
20: 000080e7 jalr ra # 1c <sin_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <sin_floatarr+0x28>
tricore#
00000000 <sin_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <sin_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <sin_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <sin_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <sin_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_sin_float
1c: 1d 00 00 00 j 1c <sin_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <sin_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <sin_floatarr+0x14>
14: R_386_PC32 aux_arr_sin_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <sin_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <sin_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <sin_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <sin_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <sin_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <sin_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_sin_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
cos_intarr#
STENCIL void cos_intarr(void) {
// Element-wise cos of int array
aux_arr_cos_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <cos_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <cos_intarr>
20: R_AARCH64_CALL26 aux_arr_cos_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <cos_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <cos_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <cos_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <cos_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <cos_intarr>
14: R_ARM_CALL aux_arr_cos_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <cos_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <cos_intarr>
20: R_ARM_CALL aux_arr_cos_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <cos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_intarr+0x20>)
a: f7ff fffe bl 0 <cos_intarr>
a: R_ARM_THM_CALL aux_arr_cos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <cos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_intarr+0x20>)
a: f7ff fffe bl 0 <cos_intarr>
a: R_ARM_THM_CALL aux_arr_cos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <cos_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <cos_intarr>
1c: R_ARM_THM_CALL aux_arr_cos_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <cos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_intarr+0x20>)
a: f7ff fffe bl 0 <cos_intarr>
a: R_ARM_THM_CALL aux_arr_cos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <cos_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <cos_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_cos_int
20: 000080e7 jalr ra # 1c <cos_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <cos_intarr+0x28>
riscv64#
0000000000000000 <cos_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <cos_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_cos_int
20: 000080e7 jalr ra # 1c <cos_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <cos_intarr+0x28>
tricore#
00000000 <cos_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <cos_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <cos_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <cos_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <cos_intarr+0x18>
18: R_TRICORE_24REL aux_arr_cos_int
1c: 1d 00 00 00 j 1c <cos_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <cos_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <cos_intarr+0x14>
14: R_386_PC32 aux_arr_cos_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <cos_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <cos_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <cos_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <cos_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <cos_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <cos_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_cos_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
cos_floatarr#
STENCIL void cos_floatarr(void) {
// Element-wise cos of float array
aux_arr_cos_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <cos_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <cos_floatarr>
20: R_AARCH64_CALL26 aux_arr_cos_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <cos_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <cos_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <cos_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <cos_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <cos_floatarr>
14: R_ARM_CALL aux_arr_cos_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <cos_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <cos_floatarr>
20: R_ARM_CALL aux_arr_cos_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <cos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_floatarr+0x20>)
a: f7ff fffe bl 0 <cos_floatarr>
a: R_ARM_THM_CALL aux_arr_cos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <cos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_floatarr+0x20>)
a: f7ff fffe bl 0 <cos_floatarr>
a: R_ARM_THM_CALL aux_arr_cos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <cos_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <cos_floatarr>
1c: R_ARM_THM_CALL aux_arr_cos_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <cos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <cos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <cos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <cos_floatarr+0x20>)
a: f7ff fffe bl 0 <cos_floatarr>
a: R_ARM_THM_CALL aux_arr_cos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <cos_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <cos_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_cos_float
20: 000080e7 jalr ra # 1c <cos_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <cos_floatarr+0x28>
riscv64#
0000000000000000 <cos_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <cos_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_cos_float
20: 000080e7 jalr ra # 1c <cos_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <cos_floatarr+0x28>
tricore#
00000000 <cos_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <cos_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <cos_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <cos_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <cos_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_cos_float
1c: 1d 00 00 00 j 1c <cos_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <cos_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <cos_floatarr+0x14>
14: R_386_PC32 aux_arr_cos_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <cos_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <cos_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <cos_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <cos_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <cos_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <cos_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_cos_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
tan_intarr#
STENCIL void tan_intarr(void) {
// Element-wise tan of int array
aux_arr_tan_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <tan_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <tan_intarr>
20: R_AARCH64_CALL26 aux_arr_tan_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <tan_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <tan_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <tan_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <tan_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <tan_intarr>
14: R_ARM_CALL aux_arr_tan_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <tan_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <tan_intarr>
20: R_ARM_CALL aux_arr_tan_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <tan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_intarr+0x20>)
a: f7ff fffe bl 0 <tan_intarr>
a: R_ARM_THM_CALL aux_arr_tan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <tan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_intarr+0x20>)
a: f7ff fffe bl 0 <tan_intarr>
a: R_ARM_THM_CALL aux_arr_tan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <tan_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <tan_intarr>
1c: R_ARM_THM_CALL aux_arr_tan_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <tan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_intarr+0x20>)
a: f7ff fffe bl 0 <tan_intarr>
a: R_ARM_THM_CALL aux_arr_tan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <tan_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <tan_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tan_int
20: 000080e7 jalr ra # 1c <tan_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tan_intarr+0x28>
riscv64#
0000000000000000 <tan_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <tan_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tan_int
20: 000080e7 jalr ra # 1c <tan_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tan_intarr+0x28>
tricore#
00000000 <tan_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <tan_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <tan_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <tan_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <tan_intarr+0x18>
18: R_TRICORE_24REL aux_arr_tan_int
1c: 1d 00 00 00 j 1c <tan_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <tan_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <tan_intarr+0x14>
14: R_386_PC32 aux_arr_tan_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <tan_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <tan_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <tan_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <tan_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <tan_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <tan_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_tan_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
tan_floatarr#
STENCIL void tan_floatarr(void) {
// Element-wise tan of float array
aux_arr_tan_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <tan_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <tan_floatarr>
20: R_AARCH64_CALL26 aux_arr_tan_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <tan_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <tan_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <tan_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <tan_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <tan_floatarr>
14: R_ARM_CALL aux_arr_tan_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <tan_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <tan_floatarr>
20: R_ARM_CALL aux_arr_tan_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <tan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_floatarr+0x20>)
a: f7ff fffe bl 0 <tan_floatarr>
a: R_ARM_THM_CALL aux_arr_tan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <tan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_floatarr+0x20>)
a: f7ff fffe bl 0 <tan_floatarr>
a: R_ARM_THM_CALL aux_arr_tan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <tan_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <tan_floatarr>
1c: R_ARM_THM_CALL aux_arr_tan_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <tan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tan_floatarr+0x20>)
a: f7ff fffe bl 0 <tan_floatarr>
a: R_ARM_THM_CALL aux_arr_tan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <tan_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <tan_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tan_float
20: 000080e7 jalr ra # 1c <tan_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tan_floatarr+0x28>
riscv64#
0000000000000000 <tan_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <tan_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tan_float
20: 000080e7 jalr ra # 1c <tan_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tan_floatarr+0x28>
tricore#
00000000 <tan_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <tan_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <tan_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <tan_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <tan_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_tan_float
1c: 1d 00 00 00 j 1c <tan_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <tan_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <tan_floatarr+0x14>
14: R_386_PC32 aux_arr_tan_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <tan_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <tan_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <tan_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <tan_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <tan_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <tan_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_tan_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
asin_intarr#
STENCIL void asin_intarr(void) {
// Element-wise asin of int array
aux_arr_asin_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <asin_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <asin_intarr>
20: R_AARCH64_CALL26 aux_arr_asin_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <asin_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <asin_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <asin_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <asin_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <asin_intarr>
14: R_ARM_CALL aux_arr_asin_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <asin_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <asin_intarr>
20: R_ARM_CALL aux_arr_asin_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <asin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_intarr+0x20>)
a: f7ff fffe bl 0 <asin_intarr>
a: R_ARM_THM_CALL aux_arr_asin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <asin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_intarr+0x20>)
a: f7ff fffe bl 0 <asin_intarr>
a: R_ARM_THM_CALL aux_arr_asin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <asin_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <asin_intarr>
1c: R_ARM_THM_CALL aux_arr_asin_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <asin_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_intarr+0x20>)
a: f7ff fffe bl 0 <asin_intarr>
a: R_ARM_THM_CALL aux_arr_asin_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <asin_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <asin_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_asin_int
20: 000080e7 jalr ra # 1c <asin_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <asin_intarr+0x28>
riscv64#
0000000000000000 <asin_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <asin_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_asin_int
20: 000080e7 jalr ra # 1c <asin_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <asin_intarr+0x28>
tricore#
00000000 <asin_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <asin_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <asin_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <asin_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <asin_intarr+0x18>
18: R_TRICORE_24REL aux_arr_asin_int
1c: 1d 00 00 00 j 1c <asin_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <asin_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <asin_intarr+0x14>
14: R_386_PC32 aux_arr_asin_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <asin_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <asin_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <asin_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <asin_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <asin_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <asin_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_asin_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
asin_floatarr#
STENCIL void asin_floatarr(void) {
// Element-wise asin of float array
aux_arr_asin_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <asin_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <asin_floatarr>
20: R_AARCH64_CALL26 aux_arr_asin_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <asin_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <asin_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <asin_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <asin_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <asin_floatarr>
14: R_ARM_CALL aux_arr_asin_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <asin_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <asin_floatarr>
20: R_ARM_CALL aux_arr_asin_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <asin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_floatarr+0x20>)
a: f7ff fffe bl 0 <asin_floatarr>
a: R_ARM_THM_CALL aux_arr_asin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <asin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_floatarr+0x20>)
a: f7ff fffe bl 0 <asin_floatarr>
a: R_ARM_THM_CALL aux_arr_asin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <asin_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <asin_floatarr>
1c: R_ARM_THM_CALL aux_arr_asin_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <asin_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <asin_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <asin_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <asin_floatarr+0x20>)
a: f7ff fffe bl 0 <asin_floatarr>
a: R_ARM_THM_CALL aux_arr_asin_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <asin_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <asin_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_asin_float
20: 000080e7 jalr ra # 1c <asin_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <asin_floatarr+0x28>
riscv64#
0000000000000000 <asin_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <asin_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_asin_float
20: 000080e7 jalr ra # 1c <asin_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <asin_floatarr+0x28>
tricore#
00000000 <asin_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <asin_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <asin_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <asin_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <asin_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_asin_float
1c: 1d 00 00 00 j 1c <asin_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <asin_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <asin_floatarr+0x14>
14: R_386_PC32 aux_arr_asin_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <asin_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <asin_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <asin_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <asin_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <asin_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <asin_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_asin_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
acos_intarr#
STENCIL void acos_intarr(void) {
// Element-wise acos of int array
aux_arr_acos_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <acos_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <acos_intarr>
20: R_AARCH64_CALL26 aux_arr_acos_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <acos_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <acos_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <acos_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <acos_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <acos_intarr>
14: R_ARM_CALL aux_arr_acos_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <acos_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <acos_intarr>
20: R_ARM_CALL aux_arr_acos_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <acos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_intarr+0x20>)
a: f7ff fffe bl 0 <acos_intarr>
a: R_ARM_THM_CALL aux_arr_acos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <acos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_intarr+0x20>)
a: f7ff fffe bl 0 <acos_intarr>
a: R_ARM_THM_CALL aux_arr_acos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <acos_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <acos_intarr>
1c: R_ARM_THM_CALL aux_arr_acos_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <acos_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_intarr+0x20>)
a: f7ff fffe bl 0 <acos_intarr>
a: R_ARM_THM_CALL aux_arr_acos_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <acos_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <acos_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_acos_int
20: 000080e7 jalr ra # 1c <acos_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <acos_intarr+0x28>
riscv64#
0000000000000000 <acos_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <acos_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_acos_int
20: 000080e7 jalr ra # 1c <acos_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <acos_intarr+0x28>
tricore#
00000000 <acos_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <acos_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <acos_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <acos_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <acos_intarr+0x18>
18: R_TRICORE_24REL aux_arr_acos_int
1c: 1d 00 00 00 j 1c <acos_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <acos_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <acos_intarr+0x14>
14: R_386_PC32 aux_arr_acos_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <acos_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <acos_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <acos_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <acos_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <acos_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <acos_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_acos_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
acos_floatarr#
STENCIL void acos_floatarr(void) {
// Element-wise acos of float array
aux_arr_acos_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <acos_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <acos_floatarr>
20: R_AARCH64_CALL26 aux_arr_acos_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <acos_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <acos_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <acos_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <acos_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <acos_floatarr>
14: R_ARM_CALL aux_arr_acos_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <acos_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <acos_floatarr>
20: R_ARM_CALL aux_arr_acos_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <acos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_floatarr+0x20>)
a: f7ff fffe bl 0 <acos_floatarr>
a: R_ARM_THM_CALL aux_arr_acos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <acos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_floatarr+0x20>)
a: f7ff fffe bl 0 <acos_floatarr>
a: R_ARM_THM_CALL aux_arr_acos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <acos_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <acos_floatarr>
1c: R_ARM_THM_CALL aux_arr_acos_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <acos_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <acos_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <acos_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <acos_floatarr+0x20>)
a: f7ff fffe bl 0 <acos_floatarr>
a: R_ARM_THM_CALL aux_arr_acos_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <acos_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <acos_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_acos_float
20: 000080e7 jalr ra # 1c <acos_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <acos_floatarr+0x28>
riscv64#
0000000000000000 <acos_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <acos_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_acos_float
20: 000080e7 jalr ra # 1c <acos_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <acos_floatarr+0x28>
tricore#
00000000 <acos_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <acos_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <acos_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <acos_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <acos_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_acos_float
1c: 1d 00 00 00 j 1c <acos_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <acos_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <acos_floatarr+0x14>
14: R_386_PC32 aux_arr_acos_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <acos_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <acos_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <acos_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <acos_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <acos_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <acos_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_acos_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
atan_intarr#
STENCIL void atan_intarr(void) {
// Element-wise atan of int array
aux_arr_atan_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <atan_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <atan_intarr>
20: R_AARCH64_CALL26 aux_arr_atan_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <atan_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <atan_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <atan_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <atan_intarr>
14: R_ARM_CALL aux_arr_atan_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <atan_intarr>
20: R_ARM_CALL aux_arr_atan_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_intarr+0x20>)
a: f7ff fffe bl 0 <atan_intarr>
a: R_ARM_THM_CALL aux_arr_atan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_intarr+0x20>)
a: f7ff fffe bl 0 <atan_intarr>
a: R_ARM_THM_CALL aux_arr_atan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <atan_intarr>
1c: R_ARM_THM_CALL aux_arr_atan_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_intarr+0x20>)
a: f7ff fffe bl 0 <atan_intarr>
a: R_ARM_THM_CALL aux_arr_atan_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <atan_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_atan_int
20: 000080e7 jalr ra # 1c <atan_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <atan_intarr+0x28>
riscv64#
0000000000000000 <atan_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <atan_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_atan_int
20: 000080e7 jalr ra # 1c <atan_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <atan_intarr+0x28>
tricore#
00000000 <atan_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <atan_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <atan_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <atan_intarr+0x18>
18: R_TRICORE_24REL aux_arr_atan_int
1c: 1d 00 00 00 j 1c <atan_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <atan_intarr+0x14>
14: R_386_PC32 aux_arr_atan_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <atan_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <atan_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <atan_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <atan_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_atan_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
atan_floatarr#
STENCIL void atan_floatarr(void) {
// Element-wise atan of float array
aux_arr_atan_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <atan_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <atan_floatarr>
20: R_AARCH64_CALL26 aux_arr_atan_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <atan_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <atan_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <atan_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <atan_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <atan_floatarr>
14: R_ARM_CALL aux_arr_atan_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <atan_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <atan_floatarr>
20: R_ARM_CALL aux_arr_atan_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <atan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_floatarr+0x20>)
a: f7ff fffe bl 0 <atan_floatarr>
a: R_ARM_THM_CALL aux_arr_atan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <atan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_floatarr+0x20>)
a: f7ff fffe bl 0 <atan_floatarr>
a: R_ARM_THM_CALL aux_arr_atan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <atan_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <atan_floatarr>
1c: R_ARM_THM_CALL aux_arr_atan_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <atan_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <atan_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <atan_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <atan_floatarr+0x20>)
a: f7ff fffe bl 0 <atan_floatarr>
a: R_ARM_THM_CALL aux_arr_atan_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <atan_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <atan_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_atan_float
20: 000080e7 jalr ra # 1c <atan_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <atan_floatarr+0x28>
riscv64#
0000000000000000 <atan_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <atan_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_atan_float
20: 000080e7 jalr ra # 1c <atan_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <atan_floatarr+0x28>
tricore#
00000000 <atan_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <atan_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <atan_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <atan_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <atan_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_atan_float
1c: 1d 00 00 00 j 1c <atan_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <atan_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <atan_floatarr+0x14>
14: R_386_PC32 aux_arr_atan_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <atan_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <atan_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <atan_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <atan_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <atan_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <atan_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_atan_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
tanh_intarr#
STENCIL void tanh_intarr(void) {
// Element-wise tanh of int array
aux_arr_tanh_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <tanh_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <tanh_intarr>
20: R_AARCH64_CALL26 aux_arr_tanh_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <tanh_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <tanh_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <tanh_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <tanh_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <tanh_intarr>
14: R_ARM_CALL aux_arr_tanh_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <tanh_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <tanh_intarr>
20: R_ARM_CALL aux_arr_tanh_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <tanh_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_intarr+0x20>)
a: f7ff fffe bl 0 <tanh_intarr>
a: R_ARM_THM_CALL aux_arr_tanh_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <tanh_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_intarr+0x20>)
a: f7ff fffe bl 0 <tanh_intarr>
a: R_ARM_THM_CALL aux_arr_tanh_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <tanh_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <tanh_intarr>
1c: R_ARM_THM_CALL aux_arr_tanh_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <tanh_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_intarr+0x20>)
a: f7ff fffe bl 0 <tanh_intarr>
a: R_ARM_THM_CALL aux_arr_tanh_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <tanh_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <tanh_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tanh_int
20: 000080e7 jalr ra # 1c <tanh_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tanh_intarr+0x28>
riscv64#
0000000000000000 <tanh_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <tanh_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tanh_int
20: 000080e7 jalr ra # 1c <tanh_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tanh_intarr+0x28>
tricore#
00000000 <tanh_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <tanh_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <tanh_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <tanh_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <tanh_intarr+0x18>
18: R_TRICORE_24REL aux_arr_tanh_int
1c: 1d 00 00 00 j 1c <tanh_intarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <tanh_intarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <tanh_intarr+0x14>
14: R_386_PC32 aux_arr_tanh_int
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <tanh_intarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <tanh_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <tanh_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <tanh_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <tanh_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <tanh_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_tanh_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
tanh_floatarr#
STENCIL void tanh_floatarr(void) {
// Element-wise tanh of float array
aux_arr_tanh_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <tanh_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <tanh_floatarr>
20: R_AARCH64_CALL26 aux_arr_tanh_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <tanh_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <tanh_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <tanh_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <tanh_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <tanh_floatarr>
14: R_ARM_CALL aux_arr_tanh_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <tanh_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <tanh_floatarr>
20: R_ARM_CALL aux_arr_tanh_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <tanh_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_floatarr+0x20>)
a: f7ff fffe bl 0 <tanh_floatarr>
a: R_ARM_THM_CALL aux_arr_tanh_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <tanh_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_floatarr+0x20>)
a: f7ff fffe bl 0 <tanh_floatarr>
a: R_ARM_THM_CALL aux_arr_tanh_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <tanh_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <tanh_floatarr>
1c: R_ARM_THM_CALL aux_arr_tanh_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <tanh_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <tanh_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <tanh_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <tanh_floatarr+0x20>)
a: f7ff fffe bl 0 <tanh_floatarr>
a: R_ARM_THM_CALL aux_arr_tanh_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <tanh_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <tanh_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tanh_float
20: 000080e7 jalr ra # 1c <tanh_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tanh_floatarr+0x28>
riscv64#
0000000000000000 <tanh_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <tanh_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_tanh_float
20: 000080e7 jalr ra # 1c <tanh_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <tanh_floatarr+0x28>
tricore#
00000000 <tanh_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <tanh_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <tanh_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <tanh_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <tanh_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_tanh_float
1c: 1d 00 00 00 j 1c <tanh_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <tanh_floatarr>:
0: 83 ec 10 sub $0x10,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <tanh_floatarr+0x14>
14: R_386_PC32 aux_arr_tanh_float
18: 83 c4 1c add $0x1c,%esp
1b: e9 fc ff ff ff jmp 1c <tanh_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <tanh_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <tanh_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <tanh_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <tanh_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <tanh_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_tanh_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
abs_floatarr#
STENCIL void abs_floatarr(void) {
// Element-wise abs of float array
aux_arr_abs_float(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_float_ref();
}
arm64#
0000000000000000 <abs_floatarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <abs_floatarr>
20: R_AARCH64_CALL26 aux_arr_abs_float
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_float_ref>
28: R_AARCH64_JUMP26 result_float_ref
armv6#
00000000 <abs_floatarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <abs_floatarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <abs_floatarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <abs_floatarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <abs_floatarr>
14: R_ARM_CALL aux_arr_abs_float
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_float_ref>
1c: R_ARM_JUMP24 result_float_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <abs_floatarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <abs_floatarr>
20: R_ARM_CALL aux_arr_abs_float
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_float_ref>
28: R_ARM_JUMP24 result_float_ref
armv7mthumb#
00000000 <abs_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_floatarr+0x20>)
a: f7ff fffe bl 0 <abs_floatarr>
a: R_ARM_THM_CALL aux_arr_abs_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <abs_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_floatarr+0x20>)
a: f7ff fffe bl 0 <abs_floatarr>
a: R_ARM_THM_CALL aux_arr_abs_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <abs_floatarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <abs_floatarr>
1c: R_ARM_THM_CALL aux_arr_abs_float
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_float_ref>
24: R_ARM_THM_JUMP24 result_float_ref
armv81mthumb#
00000000 <abs_floatarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_floatarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_floatarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_floatarr+0x20>)
a: f7ff fffe bl 0 <abs_floatarr>
a: R_ARM_THM_CALL aux_arr_abs_float
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_float_ref>
12: R_ARM_THM_JUMP24 result_float_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <abs_floatarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <abs_floatarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_abs_float
20: 000080e7 jalr ra # 1c <abs_floatarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <abs_floatarr+0x28>
riscv64#
0000000000000000 <abs_floatarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <abs_floatarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_abs_float
20: 000080e7 jalr ra # 1c <abs_floatarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_float_ref
2c: 00030067 jr t1 # 28 <abs_floatarr+0x28>
tricore#
00000000 <abs_floatarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <abs_floatarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <abs_floatarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <abs_floatarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <abs_floatarr+0x18>
18: R_TRICORE_24REL aux_arr_abs_float
1c: 1d 00 00 00 j 1c <abs_floatarr+0x1c>
1c: R_TRICORE_24REL result_float_ref
x86#
00000000 <abs_floatarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <abs_floatarr+0x14>
14: R_386_PC32 aux_arr_abs_float
18: 83 c4 18 add $0x18,%esp
1b: e9 fc ff ff ff jmp 1c <abs_floatarr+0x1c>
1c: R_386_PC32 result_float_ref
x86_64#
0000000000000000 <abs_floatarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <abs_floatarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <abs_floatarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <abs_floatarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <abs_floatarr+0x20>
1c: R_X86_64_PLT32 aux_arr_abs_float-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_float_ref-0x4
abs_intarr#
STENCIL void abs_intarr(void) {
// Element-wise abs of int array
aux_arr_abs_int(REF(ref_arg0), REF(ref_out), *(int *)REF(ref_arg1));
result_int_ref();
}
arm64#
0000000000000000 <abs_intarr>:
0: a9bf7bfd stp x29, x30, [sp, #-16]!
4: 90000002 adrp x2, 0 <ref_arg1>
4: R_AARCH64_ADR_PREL_PG_HI21 ref_arg1
8: 90000001 adrp x1, 0 <ref_out>
8: R_AARCH64_ADR_PREL_PG_HI21 ref_out
c: 910003fd mov x29, sp
10: b9400042 ldr w2, [x2]
10: R_AARCH64_LDST32_ABS_LO12_NC ref_arg1
14: 91000021 add x1, x1, #0x0
14: R_AARCH64_ADD_ABS_LO12_NC ref_out
18: 90000000 adrp x0, 0 <ref_arg0>
18: R_AARCH64_ADR_PREL_PG_HI21 ref_arg0
1c: 91000000 add x0, x0, #0x0
1c: R_AARCH64_ADD_ABS_LO12_NC ref_arg0
20: 94000000 bl 0 <abs_intarr>
20: R_AARCH64_CALL26 aux_arr_abs_int
24: a8c17bfd ldp x29, x30, [sp], #16
28: 14000000 b 0 <result_int_ref>
28: R_AARCH64_JUMP26 result_int_ref
armv6#
00000000 <abs_intarr>:
0: e59f3018 ldr r3, [pc, #24] @ 20 <abs_intarr+0x20>
4: e92d4010 push {r4, lr}
8: e59f1014 ldr r1, [pc, #20] @ 24 <abs_intarr+0x24>
c: e59f0014 ldr r0, [pc, #20] @ 28 <abs_intarr+0x28>
10: e5932000 ldr r2, [r3]
14: ebfffffe bl 0 <abs_intarr>
14: R_ARM_CALL aux_arr_abs_int
18: e8bd4010 pop {r4, lr}
1c: eafffffe b 0 <result_int_ref>
1c: R_ARM_JUMP24 result_int_ref
...
20: R_ARM_ABS32 ref_arg1
24: R_ARM_ABS32 ref_out
28: R_ARM_ABS32 ref_arg0
armv7#
00000000 <abs_intarr>:
0: e3003000 movw r3, #0
0: R_ARM_MOVW_ABS_NC ref_arg1
4: e3403000 movt r3, #0
4: R_ARM_MOVT_ABS ref_arg1
8: e92d4010 push {r4, lr}
c: e3001000 movw r1, #0
c: R_ARM_MOVW_ABS_NC ref_out
10: e3401000 movt r1, #0
10: R_ARM_MOVT_ABS ref_out
14: e5932000 ldr r2, [r3]
18: e3000000 movw r0, #0
18: R_ARM_MOVW_ABS_NC ref_arg0
1c: e3400000 movt r0, #0
1c: R_ARM_MOVT_ABS ref_arg0
20: ebfffffe bl 0 <abs_intarr>
20: R_ARM_CALL aux_arr_abs_int
24: e8bd4010 pop {r4, lr}
28: eafffffe b 0 <result_int_ref>
28: R_ARM_JUMP24 result_int_ref
armv7mthumb#
00000000 <abs_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_intarr+0x20>)
a: f7ff fffe bl 0 <abs_intarr>
a: R_ARM_THM_CALL aux_arr_abs_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_int_ref>
12: R_ARM_THM_JUMP24 result_int_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7mthumb_fpv5#
00000000 <abs_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_intarr+0x20>)
a: f7ff fffe bl 0 <abs_intarr>
a: R_ARM_THM_CALL aux_arr_abs_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_int_ref>
12: R_ARM_THM_JUMP24 result_int_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
armv7thumb#
00000000 <abs_intarr>:
0: b508 push {r3, lr}
2: f240 0300 movw r3, #0
2: R_ARM_THM_MOVW_ABS_NC ref_arg1
6: f2c0 0300 movt r3, #0
6: R_ARM_THM_MOVT_ABS ref_arg1
a: f240 0100 movw r1, #0
a: R_ARM_THM_MOVW_ABS_NC ref_out
e: f2c0 0100 movt r1, #0
e: R_ARM_THM_MOVT_ABS ref_out
12: f240 0000 movw r0, #0
12: R_ARM_THM_MOVW_ABS_NC ref_arg0
16: f2c0 0000 movt r0, #0
16: R_ARM_THM_MOVT_ABS ref_arg0
1a: 681a ldr r2, [r3, #0]
1c: f7ff fffe bl 0 <abs_intarr>
1c: R_ARM_THM_CALL aux_arr_abs_int
20: e8bd 4008 ldmia.w sp!, {r3, lr}
24: f7ff bffe b.w 0 <result_int_ref>
24: R_ARM_THM_JUMP24 result_int_ref
armv81mthumb#
00000000 <abs_intarr>:
0: b508 push {r3, lr}
2: 4b05 ldr r3, [pc, #20] @ (18 <abs_intarr+0x18>)
4: 4905 ldr r1, [pc, #20] @ (1c <abs_intarr+0x1c>)
6: 681a ldr r2, [r3, #0]
8: 4805 ldr r0, [pc, #20] @ (20 <abs_intarr+0x20>)
a: f7ff fffe bl 0 <abs_intarr>
a: R_ARM_THM_CALL aux_arr_abs_int
e: e8bd 4008 ldmia.w sp!, {r3, lr}
12: f7ff bffe b.w 0 <result_int_ref>
12: R_ARM_THM_JUMP24 result_int_ref
16: bf00 nop
...
18: R_ARM_ABS32 ref_arg1
1c: R_ARM_ABS32 ref_out
20: R_ARM_ABS32 ref_arg0
riscv32#
00000000 <abs_intarr>:
0: 00000617 auipc a2,0x0
0: R_RISCV_PCREL_HI20 ref_arg1
4: 00062603 lw a2,0(a2) # 0 <abs_intarr>
4: R_RISCV_PCREL_LO12_I .L0
8: 1141 addi sp,sp,-16
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: c606 sw ra,12(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_abs_int
20: 000080e7 jalr ra # 1c <abs_intarr+0x1c>
24: 40b2 lw ra,12(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_int_ref
2c: 00030067 jr t1 # 28 <abs_intarr+0x28>
riscv64#
0000000000000000 <abs_intarr>:
0: 1141 addi sp,sp,-16
2: 00000617 auipc a2,0x0
2: R_RISCV_PCREL_HI20 ref_arg1
6: 00062603 lw a2,0(a2) # 2 <abs_intarr+0x2>
6: R_RISCV_PCREL_LO12_I .L0
a: 00000597 auipc a1,0x0
a: R_RISCV_PCREL_HI20 ref_out
e: 00058593 mv a1,a1
e: R_RISCV_PCREL_LO12_I .L0
12: 00000517 auipc a0,0x0
12: R_RISCV_PCREL_HI20 ref_arg0
16: 00050513 mv a0,a0
16: R_RISCV_PCREL_LO12_I .L0
1a: e406 sd ra,8(sp)
1c: 00000097 auipc ra,0x0
1c: R_RISCV_CALL_PLT aux_arr_abs_int
20: 000080e7 jalr ra # 1c <abs_intarr+0x1c>
24: 60a2 ld ra,8(sp)
26: 0141 addi sp,sp,16
28: 00000317 auipc t1,0x0
28: R_RISCV_CALL_PLT result_int_ref
2c: 00030067 jr t1 # 28 <abs_intarr+0x28>
tricore#
00000000 <abs_intarr>:
0: 91 00 00 20 movh.a %a2,0
0: R_TRICORE_HIADJ ref_arg1
4: 19 24 00 00 ld.w %d4,[%a2]0 <0 <abs_intarr>>
4: R_TRICORE_LO2 ref_arg1
8: 91 00 00 50 movh.a %a5,0
8: R_TRICORE_HIADJ ref_out
c: 91 00 00 40 movh.a %a4,0
c: R_TRICORE_HIADJ ref_arg0
10: d9 55 00 00 lea %a5,[%a5]0 <0 <abs_intarr>>
10: R_TRICORE_LO2 ref_out
14: d9 44 00 00 lea %a4,[%a4]0 <0 <abs_intarr>>
14: R_TRICORE_LO2 ref_arg0
18: 6d 00 00 00 call 18 <abs_intarr+0x18>
18: R_TRICORE_24REL aux_arr_abs_int
1c: 1d 00 00 00 j 1c <abs_intarr+0x1c>
1c: R_TRICORE_24REL result_int_ref
x86#
00000000 <abs_intarr>:
0: 83 ec 0c sub $0xc,%esp
3: ff 35 00 00 00 00 push 0x0
5: R_386_32 ref_arg1
9: 68 00 00 00 00 push $0x0
a: R_386_32 ref_out
e: 68 00 00 00 00 push $0x0
f: R_386_32 ref_arg0
13: e8 fc ff ff ff call 14 <abs_intarr+0x14>
14: R_386_PC32 aux_arr_abs_int
18: 83 c4 18 add $0x18,%esp
1b: e9 fc ff ff ff jmp 1c <abs_intarr+0x1c>
1c: R_386_PC32 result_int_ref
x86_64#
0000000000000000 <abs_intarr>:
0: 48 83 ec 08 sub $0x8,%rsp
4: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # b <abs_intarr+0xb>
7: R_X86_64_PC32 ref_arg1-0x4
b: 8b 10 mov (%rax),%edx
d: 48 8d 35 00 00 00 00 lea 0x0(%rip),%rsi # 14 <abs_intarr+0x14>
10: R_X86_64_PC32 ref_out-0x4
14: 48 8d 3d 00 00 00 00 lea 0x0(%rip),%rdi # 1b <abs_intarr+0x1b>
17: R_X86_64_PC32 ref_arg0-0x4
1b: e8 00 00 00 00 call 20 <abs_intarr+0x20>
1c: R_X86_64_PLT32 aux_arr_abs_int-0x4
20: 48 83 c4 08 add $0x8,%rsp
24: e9 00 00 00 00 jmp 29 <.LC1+0x1>
25: R_X86_64_PLT32 result_int_ref-0x4